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| author | Thomas Chou <thomas@wytron.com.tw> | 2015-11-06 09:36:52 +0800 |
|---|---|---|
| committer | Thomas Chou <thomas@wytron.com.tw> | 2015-11-06 12:56:47 +0800 |
| commit | 14fb5369909796f8de1a7fa0c8de1384d3dd2777 (patch) | |
| tree | 5d049d03d9574b296d799ce75a341287fc647ffb /drivers | |
| parent | 13146ec9380364c46dbc9473faff5707351935cc (diff) | |
| download | talos-obmc-uboot-14fb5369909796f8de1a7fa0c8de1384d3dd2777.tar.gz talos-obmc-uboot-14fb5369909796f8de1a7fa0c8de1384d3dd2777.zip | |
net: altera_tse: remove the useless parenthesis
Remove the useless parenthesis.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Chin Liang See <clsee@altera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/altera_tse.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h index 78ae369120..0981308a87 100644 --- a/drivers/net/altera_tse.h +++ b/drivers/net/altera_tse.h @@ -14,11 +14,11 @@ #define __packed_1_ __packed __aligned(1) /* SGDMA Stuff */ -#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010) +#define ALT_SGDMA_STATUS_BUSY_MSK 0x00000010 -#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020) -#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040) -#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000) +#define ALT_SGDMA_CONTROL_RUN_MSK 0x00000020 +#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK 0x00000040 +#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK 0x00010000 /* * Descriptor control bit masks & offsets @@ -27,10 +27,10 @@ * The following bit-offsets are expressed relative to the LSB of * the control register bitfield. */ -#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001) -#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002) -#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004) -#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK 0x00000001 +#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK 0x00000002 +#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK 0x00000004 +#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK 0x00000080 /* * Descriptor status bit masks & offsets @@ -39,7 +39,7 @@ * The following bit-offsets are expressed relative to the LSB of * the status register bitfield. */ -#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080) +#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK 0x00000080 /* * The SGDMA controller buffer descriptor allocates @@ -85,12 +85,12 @@ struct alt_sgdma_registers { }; /* TSE Stuff */ -#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001) -#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002) -#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008) -#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400) -#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000) -#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000) +#define ALTERA_TSE_CMD_TX_ENA_MSK 0x00000001 +#define ALTERA_TSE_CMD_RX_ENA_MSK 0x00000002 +#define ALTERA_TSE_CMD_ETH_SPEED_MSK 0x00000008 +#define ALTERA_TSE_CMD_HD_ENA_MSK 0x00000400 +#define ALTERA_TSE_CMD_SW_RESET_MSK 0x00002000 +#define ALTERA_TSE_CMD_ENA_10_MSK 0x02000000 #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ) #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ) |
