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authorStephen Warren <swarren@nvidia.com>2016-06-17 09:44:00 -0600
committerSimon Glass <sjg@chromium.org>2016-06-19 17:05:55 -0600
commit135aa95002646c46e89de93fa36adad1b010548f (patch)
treeb601e08f7d91c7e2cda127d59f8f81128d0cb1ac /drivers/video/rockchip/rk_edp.c
parent4581b717b1bf0fb04e7d9fcaf3d4c23d357154ac (diff)
downloadtalos-obmc-uboot-135aa95002646c46e89de93fa36adad1b010548f.tar.gz
talos-obmc-uboot-135aa95002646c46e89de93fa36adad1b010548f.zip
clk: convert API to match reset/mailbox style
The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/video/rockchip/rk_edp.c')
-rw-r--r--drivers/video/rockchip/rk_edp.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 124ddf684b..7ece038c8f 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -1009,8 +1009,7 @@ int rk_edp_probe(struct udevice *dev)
struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
struct rk_edp_priv *priv = dev_get_priv(dev);
struct rk3288_edp *regs = priv->regs;
- struct udevice *clk;
- int periph;
+ struct clk clk;
int ret;
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
@@ -1026,8 +1025,8 @@ int rk_edp_probe(struct udevice *dev)
ret = clk_get_by_index(dev, 1, &clk);
if (ret >= 0) {
- periph = ret;
- ret = clk_set_periph_rate(clk, periph, 0);
+ ret = clk_set_rate(&clk, 0);
+ clk_free(&clk);
}
if (ret) {
debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
@@ -1036,8 +1035,8 @@ int rk_edp_probe(struct udevice *dev)
ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
if (ret >= 0) {
- periph = ret;
- ret = clk_set_periph_rate(clk, periph, 192000000);
+ ret = clk_set_rate(&clk, 192000000);
+ clk_free(&clk);
}
if (ret < 0) {
debug("%s: Failed to set clock in source device '%s': ret=%d\n",
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