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author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-10-14 10:46:36 +0200 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2015-10-14 10:46:36 +0200 |
commit | 13a3972585af60ec367d209cedbd3601e0c77467 (patch) | |
tree | 4b3312669b3e501f6bc10b39d8c7bbf516f07aac /drivers/pci/pcie_imx.c | |
parent | 208bd51396fb606dbdcf45b064e6b372d7dd3e81 (diff) | |
parent | 297faccca2235e359012118495b9b73451d54bb9 (diff) | |
download | talos-obmc-uboot-13a3972585af60ec367d209cedbd3601e0c77467.tar.gz talos-obmc-uboot-13a3972585af60ec367d209cedbd3601e0c77467.zip |
Merge remote-tracking branch 'u-boot/master'
Diffstat (limited to 'drivers/pci/pcie_imx.c')
-rw-r--r-- | drivers/pci/pcie_imx.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index ca485ba90c..1568f20c1a 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -495,7 +495,7 @@ __weak int imx6_pcie_toggle_reset(void) * * The PCIe #PERST reset line _MUST_ be connected, otherwise your * design does not conform to the specification. You must wait at - * least 20 mS after de-asserting the #PERST so the EP device can + * least 20 ms after de-asserting the #PERST so the EP device can * do self-initialisation. * * In case your #PERST pin is connected to a plain GPIO pin of the @@ -506,7 +506,7 @@ __weak int imx6_pcie_toggle_reset(void) * In case your #PERST toggling logic is more complex, for example * connected via CPLD or somesuch, you can override this function * in your board file and implement reset logic as needed. You must - * not forget to wait at least 20 mS after de-asserting #PERST in + * not forget to wait at least 20 ms after de-asserting #PERST in * this case either though. * * In case your #PERST line of the PCIe EP device is not connected @@ -538,7 +538,7 @@ static int imx6_pcie_deassert_core_reset(void) /* * Wait for the clock to settle a bit, when the clock are sourced - * from the CPU, we need about 30mS to settle. + * from the CPU, we need about 30 ms to settle. */ mdelay(50); |