diff options
| author | Ye Li <ye.li@nxp.com> | 2016-06-15 10:53:01 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-28 12:08:53 -0700 |
| commit | 84ecdf6da9eb102b2de87d5912d1554f44d33237 (patch) | |
| tree | 38530fee427d50204ab35c1c181e2ca5744e4d5f /drivers/mmc | |
| parent | f53225cce406058c09cf81456d9dc4956fef1b73 (diff) | |
| download | talos-obmc-uboot-84ecdf6da9eb102b2de87d5912d1554f44d33237.tar.gz talos-obmc-uboot-84ecdf6da9eb102b2de87d5912d1554f44d33237.zip | |
fsl_esdhc: Update clock enable bits for USDHC
The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
external card and reinitialize it.
So in this patch, we change to use the vendorspec registers for these bits
operation.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index bfbef66d86..c5f08ea08b 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -538,7 +538,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); #else esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); #endif @@ -548,7 +548,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) udelay(10000); #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); #else esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -643,6 +643,8 @@ static int esdhc_init(struct mmc *mmc) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); +#else + esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); #endif /* Set the initial clock speed */ @@ -740,6 +742,9 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); +#else + esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | + VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); #endif writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); |
