diff options
| author | Simon Glass <sjg@chromium.org> | 2016-03-06 19:28:13 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-03-17 10:27:23 +0800 |
| commit | d6d50db8a32674e56d4464688b1d74c9edaab550 (patch) | |
| tree | 8c665fe4cc09d214271a724875adeae7b88caa14 /drivers/gpio/intel_ich6_gpio.c | |
| parent | 963a811ab42aac2fac6fc063dc7cc689a3336d28 (diff) | |
| download | talos-obmc-uboot-d6d50db8a32674e56d4464688b1d74c9edaab550.tar.gz talos-obmc-uboot-d6d50db8a32674e56d4464688b1d74c9edaab550.zip | |
x86: gpio: Correct GPIO setup ordering
The Intel GPIO driver can set up the GPIO pin mapping when the first GPIO
is probed. However, it assumes that the first GPIO to be probed is in the
first GPIO bank. If this is not the case then the init will write to the
wrong registers.
Fix this. Also add a note that this code is deprecated. We should move to
using device tree instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'drivers/gpio/intel_ich6_gpio.c')
| -rw-r--r-- | drivers/gpio/intel_ich6_gpio.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 527ed6d0fa..c81d0332c4 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -279,6 +279,7 @@ static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) debug("%s: Invalid register offset %d\n", __func__, offset); return -EINVAL; } + plat->offset = offset; plat->base_addr = gpiobase + offset; plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, "bank-name", NULL); @@ -293,7 +294,8 @@ static int ich6_gpio_probe(struct udevice *dev) struct ich6_bank_priv *bank = dev_get_priv(dev); if (gd->arch.gpio_map) { - setup_pch_gpios(plat->base_addr, gd->arch.gpio_map); + setup_pch_gpios(plat->base_addr - plat->offset, + gd->arch.gpio_map); gd->arch.gpio_map = NULL; } |
