summaryrefslogtreecommitdiffstats
path: root/drivers/ddr/fsl
diff options
context:
space:
mode:
authorYork Sun <yorksun@freescale.com>2014-09-11 13:32:06 -0700
committerYork Sun <yorksun@freescale.com>2014-09-25 08:36:20 -0700
commitf80d6472b47e73e35e4eaed6fc56ce5df2c82cdb (patch)
tree0d8686b5543a221089465049b6366fc993b826a1 /drivers/ddr/fsl
parent8aeb893a8ed97bac679149386cec53b275be3715 (diff)
downloadtalos-obmc-uboot-f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb.tar.gz
talos-obmc-uboot-f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb.zip
driver/ddr/fsl: Fix DDR4 driver
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl')
-rw-r--r--drivers/ddr/fsl/ctrl_regs.c9
-rw-r--r--drivers/ddr/fsl/fsl_ddr_gen4.c3
2 files changed, 8 insertions, 4 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index a5ef40f8f3..9a156bfd5e 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1902,9 +1902,12 @@ static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
}
+/* This function needs to be called after set_ddr_sdram_cfg() is called */
static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
const dimm_params_t *dimm_params)
{
+ unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
+
ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
((dimm_params->dq_mapping[1] & 0x3F) << 20) |
((dimm_params->dq_mapping[2] & 0x3F) << 14) |
@@ -1923,9 +1926,11 @@ static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
((dimm_params->dq_mapping[15] & 0x3F) << 8) |
((dimm_params->dq_mapping[16] & 0x3F) << 2);
+ /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
((dimm_params->dq_mapping[8] & 0x3F) << 20) |
- ((dimm_params->dq_mapping[9] & 0x3F) << 14) |
+ (acc_ecc_en ? 0 :
+ (dimm_params->dq_mapping[9] & 0x3F) << 14) |
dimm_params->dq_mapping_ors;
debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
@@ -2292,7 +2297,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
if (ip_rev > 0x40400)
unq_mrs_en = 1;
- if (ip_rev > 0x40700)
+ if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
ddr->debug[18] = popts->cswl_override;
set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index bfc76b3485..e024db9ee2 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -216,7 +216,7 @@ step2:
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
* Let's wait for 800ms
*/
- bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+ bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
(get_ddr_freq(0) >> 20)) << 2;
@@ -233,5 +233,4 @@ step2:
if (timeout <= 0)
printf("Waiting for D_INIT timeout. Memory may not work.\n");
-
}
OpenPOWER on IntegriCloud