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authorYork Sun <yorksun@freescale.com>2014-09-11 13:32:06 -0700
committerYork Sun <yorksun@freescale.com>2014-09-25 08:36:20 -0700
commitf80d6472b47e73e35e4eaed6fc56ce5df2c82cdb (patch)
tree0d8686b5543a221089465049b6366fc993b826a1 /drivers/ddr/fsl/fsl_ddr_gen4.c
parent8aeb893a8ed97bac679149386cec53b275be3715 (diff)
downloadtalos-obmc-uboot-f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb.tar.gz
talos-obmc-uboot-f80d6472b47e73e35e4eaed6fc56ce5df2c82cdb.zip
driver/ddr/fsl: Fix DDR4 driver
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/fsl_ddr_gen4.c')
-rw-r--r--drivers/ddr/fsl/fsl_ddr_gen4.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index bfc76b3485..e024db9ee2 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -216,7 +216,7 @@ step2:
* For example, 2GB on 666MT/s 64-bit bus takes about 402ms
* Let's wait for 800ms
*/
- bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+ bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
>> SDRAM_CFG_DBW_SHIFT);
timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
(get_ddr_freq(0) >> 20)) << 2;
@@ -233,5 +233,4 @@ step2:
if (timeout <= 0)
printf("Waiting for D_INIT timeout. Memory may not work.\n");
-
}
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