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| author | Marek Vasut <marex@denx.de> | 2015-08-01 20:14:11 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:26 +0200 |
| commit | 9a48a9ac6cf5d647e38bdf43b91fe751e5415f6e (patch) | |
| tree | 895ace342b6c4be1b2b67b0513f943b0e47a525e /drivers/ddr/altera | |
| parent | ad2ba5d60774172c0651d6ed5e2e889251ed0d32 (diff) | |
| download | talos-obmc-uboot-9a48a9ac6cf5d647e38bdf43b91fe751e5415f6e.tar.gz talos-obmc-uboot-9a48a9ac6cf5d647e38bdf43b91fe751e5415f6e.zip | |
ddr: altera: sdram: Clean up set_sdr_mp_threshold()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'drivers/ddr/altera')
| -rw-r--r-- | drivers/ddr/altera/sdram.c | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index e41815b3a1..58fe26ef4a 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -465,23 +465,21 @@ static void set_sdr_mp_pacing(void) static void set_sdr_mp_threshold(void) { - debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); - clrsetbits_le32(&sdr_ctrl->mp_threshold0, - SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << + const u32 mp_threshold0 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_threshold1, - SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << + const u32 mp_threshold1 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB); - - clrsetbits_le32(&sdr_ctrl->mp_threshold2, - SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK, - CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << + const u32 mp_threshold2 = + (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB); -} + debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); + writel(mp_threshold0, &sdr_ctrl->mp_threshold0); + writel(mp_threshold1, &sdr_ctrl->mp_threshold1); + writel(mp_threshold2, &sdr_ctrl->mp_threshold2); +} /* Function to initialize SDRAM MMR */ unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) |
