path: root/doc
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authorSimon Glass <>2016-03-16 07:44:43 -0600
committerBin Meng <>2016-03-17 10:27:27 +0800
commit374e78efb0c6739c8c700325acca769d7a9e47de (patch)
tree4e626abc6d6bd43beec4b8bdad9025b4ef0e08e7 /doc
parente5aa8a9b1593f524af07318d4e84352b06a53402 (diff)
x86: Add support for the samus chromebook
This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <> Reviewed-by: Bin Meng <>
Diffstat (limited to 'doc')
1 files changed, 81 insertions, 0 deletions
diff --git a/doc/README.x86 b/doc/README.x86
index 5b51559f41..c5c3010ee2 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -105,6 +105,87 @@ $ make all
+Chromebook Samus (2015 Pixel) instructions for bare mode:
+First, you need the following binary blobs:
+* descriptor.bin - Intel flash descriptor
+* me.bin - Intel Management Engine
+* mrc.bin - Memory Reference Code, which sets up SDRAM
+* refcode.elf - Additional Reference code
+* vga.bin - video ROM, which sets up the display
+If you have a samus you can obtain them from your flash, for example, in
+developer mode on the Chromebook (use Ctrl-Alt-F2 to obtain a terminal and
+log in as 'root'):
+ cd /tmp
+ flashrom -w samus.bin
+ scp samus.bin username@ip_address:/path/to/somewhere
+If not see the coreboot tree [4] where you can use:
+ bash samus
+to get the image. There is also an '' scripts that you can use
+on the 'coreboot-Google_Samus.*' file to short-circuit some of the below.
+Then 'ifdtool -x samus.bin' on your development machine will produce:
+ flashregion_0_flashdescriptor.bin
+ flashregion_1_bios.bin
+ flashregion_2_intel_me.bin
+Rename flashregion_0_flashdescriptor.bin to descriptor.bin
+Rename flashregion_2_intel_me.bin to me.bin
+You can ignore flashregion_1_bios.bin - it is not used.
+To get the rest, use 'cbfstool samus.bin print':
+samus.bin: 8192 kB, bootblocksize 2864, romsize 8388608, offset 0x700000
+alignment: 64 bytes, architecture: x86
+Name Offset Type Size
+cmos_layout.bin 0x700000 cmos_layout 1164
+pci8086,0406.rom 0x7004c0 optionrom 65536
+spd.bin 0x710500 (unknown) 4096
+cpu_microcode_blob.bin 0x711540 microcode 70720
+fallback/romstage 0x722a00 stage 54210
+fallback/ramstage 0x72fe00 stage 96382
+config 0x7476c0 raw 6075
+fallback/vboot 0x748ec0 stage 15980
+fallback/refcode 0x74cd80 stage 75578
+fallback/payload 0x75f500 payload 62878
+u-boot.dtb 0x76eb00 (unknown) 5318
+(empty) 0x770000 null 196504
+mrc.bin 0x79ffc0 (unknown) 222876
+(empty) 0x7d66c0 null 167320
+You can extract what you need:
+ cbfstool samus.bin extract -n pci8086,0406.rom -f vga.bin
+ cbfstool samus.bin extract -n fallback/refcode -f refcode.rmod
+ cbfstool samus.bin extract -n mrc.bin -f mrc.bin
+ cbfstool samus.bin extract -n fallback/refcode -f refcode.bin -U
+Note that the -U flag is only supported by the latest cbfstool. It unpacks
+and decompresses the stage to produce a coreboot rmodule. This is a simple
+representation of an ELF file. You need the patch "Support decoding a stage
+with compression".
+Put all 5 files into board/google/chromebook_samus.
+Now you can build U-Boot and obtain u-boot.rom:
+$ make chromebook_link_defconfig
+$ make all
+If you are using em100, then this command will flash write -Boot:
+ em100 -s -d filename.rom -c W25Q64CV -r
Intel Crown Bay specific instructions for bare mode:
U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
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