nios: remove nios-32 arch

The nios-32 arch is obsolete and broken. So it is removed.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>

13 files changed, 1 insertions, 3291 deletions

diff --git a/doc/README.adnpesc1 b/doc/README.adnpesc1
deleted file mode 100644
index f9566b8ee8..0000000000
--- a/doc/README.adnpesc1
+++ /dev/null
@@ -1,235 +0,0 @@
-
-	      SSV ADNP/ESC1 Embedded Softcore Computing
-		 Nios Softcore, Altera Cyclone FPGA
-
-		    Last Update: February 27, 2004
-====================================================================
-
-This file contains information regarding U-Boot and the SSV Embedded
-Nios Softcore Computing platform ADNP/ESC1. For general Nios
-information see doc/README.nios.
-
-Most stuff of this file was borrowed and based on README.dk1s10,
-the Altera DK-1S10 related information file.
-
-For those interested in contributing ... see HELP WANTED section
-in doc/README.nios.
-
-Contents:
-
-	1. Files
-	2. Memory Organization
-	3. CPU Variations
-	4. Examples
-	5. Programming U-Boot into FLASH with GERMS
-	6. Autoboot
-	7. U-Boot environment convention and update philosophy
-
-====================================================================
-
-1. Files
-=========
-	board/ssv/adnpesc1/*
-	include/configs/ADNPESC1.h
-	include/configs/ADNPESC1_base_32.h
-
-
-2. Memory Organization
-=======================
-
-For the most part, you can put things pretty much anywhere.
-This is pretty flexible for Nios. So here we make some arbitrary
-choices & assume that the monitor is placed at the end of a memory
-resource. So you must make sure TEXT_BASE is chosen appropriately.
-This is very important if you plan to move your memory to another
-place as configured at this time!
-
-	-The heap is placed below the monitor (U-Boot code).
-	-Global data is placed below the heap.
-	-The stack is placed below global data (&grows down).
-
-(see doc/README.adnpesc1_base32 too)
-
-
-3. CPU Variations
-=================
-
-There are more than one NIOS CPU variation for the ADNP/ESC1 possible.
-U-Boot supports the following CPU configurations:
-
-	- SSV Basis 32 (make ADNPESC1_base_32_config)
-	- SSV Basis 32 at DNP evaluation base board 2
-	  (make ADNPESC1_DNPEVA2_base_32_config)
-
-
-4. Examples
-============
-
-The hello_world example works fine. To try out you have to change
-the default load address from 0x0100_0000 to 0x0204_0000 in
-examples/Makefile (the real SDRAM for default board configuration).
-
-
-5. Programming U-Boot into FLASH with GERMS
-============================================
-
-The current version of the ADNP/ESC1 port with the default
-configuration settings occupies about 97 KBytes of flash.
-A minimal configuration occupies less than 70 KByte
-(network, SPI, POST and board command support disabled). You
-can save more memory by deactivating the Hu-Shell support and
-long command help (CONFIG_SYS_HUSH_PARSER, CONFIG_SYS_LONGHELP).
-
-To program U-Boot into the ADNP/ESC1 flash using GERMS do the
-following:
-
-1. Download U-Boot to its target run space in SDRAM:
-
-   a. Close jumper RCM_EN# and push the reset button.
-
-   b. From the command line, download U-Boot using the
-      nios-run:
-
-	$ nios-run -r u-boot.srec
-
-      NOTE: In some cases this want fail. I don't know why,
-	    but try again.
-
-This takes about 1 minute (GERMS is not very speedy here).
-After u-boot is downloaded it will be executed. You should
-see the following:
-
-    U-Boot 1.0.2 (Jan 30 2004 - 12:59:15)
-
-    CPU: Nios-32 Rev. 3.3 (0x3038)
-    Reg file size: 512 LO_LIMIT/HI_LIMIT: 1/30
-    Board: SSV DilNetPC ADNP/ESC1
-    Conf.: SSV Base 32 (nios_32)
-    In:    serial
-    Out:   serial
-    Err:   serial
-    ADNPESC1 >
-
-
-2. Quit nios-run and start your terminal application (e.g. start
-   Hyperterminal or minicom).
-
-3. Download the u-boot code to RAM. When using Hyperterminal, do the
-   following:
-
-   a. From the u-boot command prompt start a binary download to SDRAM:
-
-      at the SSV Basis 32 to SDRAM:
-
-	==> loadb 2000100
-
-   b. Download u-boot.bin using kermit.
-
-4. From the U-Boot command prompt, erase flash:
-
-   at the SSV Basis 32 from 0x1000000 to 0x103ffff:
-
-	==> protect off 1:0-3
-	==> erase 1:0-3
-
-5. Copy the binary image from SDRAM to flash:
-
-   at the SSV Basis 32 from SDRAM:
-
-	==> cp.b 2000100 1000000 $filesize
-
-U-Boot will now automatically start when the board is powered on or
-reset using the SSV Basis 32 configuration without closed RCM jumper.
-To start U-Boot with closed RCM Jumper, enter the following GERMS
-command:
-
-    + g 1000000
-
-
-6. Autoboot
-===========
-
-U-Boot will try to boot a valid Nios application from Flash. For this
-it will use the deposited Hu-Shell script in environment variable
-'bootcmd' which is looking for a valid Nios application identifier
-string in Flash and go on at even its entry address. For more
-information see the next chapter.
-
-
-7. U-Boot environment convention and update philosophy
-======================================================
-
-U-Boot for the SSV ADNP/ESC1 target knows about many environment
-variables used to control the startup process, update process for
-raw Nios applications, and optionally file system image updates.
-In default configuration there are two Hu-Shell scripts to update
-the Nios application and/or the file system image:
-
-1. Update Nios application (ex. the uCLinux kernel):
-
-	run 'appl_update'
-
-2. Update optional file system image (ex. RomFS image used by uCLinux):
-
-	run 'fs_update'
-
-The Nios application can be any programm code generated in relation
-to the Nios application identifier -- the string "Nios" at offset
-address 0x0c. To use the scripts like described above in a secure way
-you have to check-up the next environment variables:
-
-1. update_allowed
-
-	- Update switch -- must be set to '1' (one) to allow any update
-	- default is '0' (zero)
-
-	  NOTE:	You should avoid to save this variable with non zero
-		value to Flash. Otherwise it would be allow any
-		update process at any time!
-
-2. appl_entry_addr
-
-	- Nios application area start address (usually in Flash)
-	- this is the startup address for autoboot
-	- each Nios application code we want to update will be copied
-	  to this address
-	- default is CONFIG_SYS_ADNPESC1_NIOS_APPL_ENTRY
-
-3. appl_end_addr
-
-	- Nios application area end address (usually in Flash)
-	- will be used to unprotect/erase the Flash area while updating
-	- default is CONFIG_SYS_ADNPESC1_NIOS_APPL_END
-
-4. appl_ident_addr
-
-	- address of the Nios application identification string
-	- this is the address checked-up by autoboot
-	- default is CONFIG_SYS_ADNPESC1_NIOS_APPL_IDENT
-
-5. appl_ident_str
-
-	- the Nios application identification string itself
-	- default is CONFIG_SYS_ADNPESC1_NIOS_IDENTIFIER
-
-6. appl_name
-
-	- name of file we have to download/update
-	- default is ADNPESC1/base32/linux.bin
-
-7. fs_base_addr
-
-	- optionally file system area start address (usually in Flash)
-	- each file system we want to update will be copied to this address
-	- default is CONFIG_SYS_ADNPESC1_FILESYSTEM_BASE
-
-8. fs_end_addr
-
-	- optionally file system area end address (usually in Flash)
-	- will be used to unprotect/erase the Flash area while updating
-	- default is CONFIG_SYS_ADNPESC1_FILESYSTEM_END
-
-9. fs_name
-
-	- name of file we have to download/update
-	- default is ADNPESC1/base32/romfs.img
diff --git a/doc/README.adnpesc1_base32 b/doc/README.adnpesc1_base32
deleted file mode 100644
index e6fb7a47df..0000000000
--- a/doc/README.adnpesc1_base32
+++ /dev/null
@@ -1,469 +0,0 @@
-
-TODO:	specify IDE i/f
-
-
-===============================================================================
-	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
-===============================================================================
-see also [1]-[5]
-
-CPU:	"DNP_ESC1"
-	32 bit NIOS for 50 MHz
-	512 Byte for register file (30 levels)
-	with out instruction cache
-	with out data cache
-	2 KByte On Chip ROM with GERMS boot monitor
-	with out On Chip RAM
-	MSTEP multiplier
-	no Debug Core
-	no On Chip Instrumentation (OCI)
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_CLK	     = 50000000
-			CONFIG_SYS_NIOS_CPU_ICACHE	     = (not present)
-			CONFIG_SYS_NIOS_CPU_DCACHE	     = (not present)
-			CONFIG_SYS_NIOS_CPU_REG_NUMS	     = 512
-			CONFIG_SYS_NIOS_CPU_MUL	     = 0
-			CONFIG_SYS_NIOS_CPU_MSTEP	     = 1
-			CONFIG_SYS_NIOS_CPU_DBG_CORE	     = 0
-
-IRQ:	 Nr.  | used by
-	------+--------------------------------------------------------
-	 16   | TIMER0	  |  CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
-	 17   | UART0	  |  CONFIG_SYS_NIOS_CPU_UART0_IRQ  = 17
-	 18   | UART1	  |  CONFIG_SYS_NIOS_CPU_UART1_IRQ  = 18
-	 20   | LAN91C111 |  CONFIG_SYS_NIOS_CPU_LAN0_IRQ   =
-	      | PIO6	  |  CONFIG_SYS_NIOS_CPU_PIO6_IRQ   = 20
-	 25   | SPI0	  |  CONFIG_SYS_NIOS_CPU_SPI0_IRQ   = 25
-	 31   | PIO7	  |  CONFIG_SYS_NIOS_CPU_PIO7_IRQ   = 31
-	 32   | PIO8	  |  CONFIG_SYS_NIOS_CPU_PIO8_IRQ   = 32
-	 33   | PIO9	  |  CONFIG_SYS_NIOS_CPU_PIO9_IRQ   = 33
-	 34   | PIO10	  |  CONFIG_SYS_NIOS_CPU_PIO10_IRQ  = 34
-	 35   | PIO11	  |  CONFIG_SYS_NIOS_CPU_PIO11_IRQ  = 35
-	 36   | PIO12	  |  CONFIG_SYS_NIOS_CPU_PIO12_IRQ  =
-	      | IDE0	  |  CONFIG_SYS_NIOS_CPU_IDE0_IRQ   = 36
-	 37   | PIO13	  |  CONFIG_SYS_NIOS_CPU_PIO13_IRQ  =
-	      | IDE1	  |  CONFIG_SYS_NIOS_CPU_IDE1_IRQ   = 37
-
-MEMORY:	 8 MByte Flash
-	16 MByte SDRAM
-
-Timer:	TIMER0: high priority programmable timer (IRQ16)
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_TICK_TIMER	     = 0
-			CONFIG_SYS_NIOS_CPU_USER_TIMER	     = (not present)
-
-PIO:	 Nr.  | description
-	------+--------------------------------------------------------
-	 PIO0 | PORTA:      8 in/outputs for general purpose usage
-	 PIO1 | PORTB:      8 in/outputs for general purpose usage
-	 PIO2 | PORTC:      4 in/outputs for general purpose usage
-	 PIO3 | RCM:	    1 input for RCM_EN# jumper (Req.Conf.Mon.)
-	 PIO4 | WDTENA:	    1 output to enable the on-board watchdog
-	 PIO5 | WDTTRIG:    1 output to trigger the on-board watchdog
-	 PIO6 | LAN0INT:    1 input for LAN91C111 irq input (IRQ20)
-	 PIO7 | INT1:	    1 input for general purpose irq (IRQ31)
-	 PIO8 | INT2:	    1 input for general purpose irq (IRQ32)
-	 PIO9 | INT3:	    1 input for general purpose irq (IRQ33)
-	 PIO10| INT4:	    1 input for general purpose irq (IRQ34)
-	 PIO11| INT5:	    1 input for general purpose irq (IRQ35)
-	 PIO12| INT6:	    1 input for general purpose irq (IRQ36)
-	      | IDE0INT:     (same) for IDE0 irq input
-	 PIO13| INT7:	    1 input for general purpose irq (IRQ37)
-	      | IDE1INT:     (same) for IDE1 irq input
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_PORTA_PIO	     = 0
-			CONFIG_SYS_NIOS_CPU_PORTB_PIO	     = 1
-			CONFIG_SYS_NIOS_CPU_PORTC_PIO	     = 2
-			CONFIG_SYS_NIOS_CPU_RCM_PIO	     = 3
-			CONFIG_SYS_NIOS_CPU_WDTENA_PIO	     = 4
-			CONFIG_SYS_NIOS_CPU_WDTTRIG_PIO     = 5
-			CONFIG_SYS_NIOS_CPU_LED_PIO	     = (not present)
-
-UART:	UART0: fixed baudrate of 115200, fixed protocol 8N1, RTS/CTS (IRQ17)
-	UART1: fixed baudrate of 115200, fixed protocol 8N1,
-	       without handshake RTS/CTS (IRQ18)
-
-SPI:	SPI0: master capable, 1 slave selectable, 250kHz target clock,
-	      2 usec targets delay between slave select and clock,
-	      data is transferred MSB-first / LSB-last (IRQ25)
-
-LAN:	SMsC LAN91C111 with:
-	  - without offset
-	  - data bus width 16 bit (on-board hard wired at 32 bit bus)
-	  - !!! 32 bit bus access --> each address * 2 !!!
-
-IDE:	(TODO)
-
-
-===============================================================================
-	M E M O R Y   M A P
-===============================================================================
-
-- - - - - - - - - - -  external extension - - - - - - - - - - - - - - - - - - -
-
-  0x44000000 ---32-----------16|15------------0-
-	       |	       |	       | \
-	       :  (real size   :	       : |
-  EXT3 (CS4)   :   and content :	       :  > CONFIG_SYS_NIOS_CPU_CS3_SIZE
-	       :   unknown)    :	       : |   = 0x01000000
-	       |	       |	       | /
-  0x43000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_CS3_BASE
-	       |	       |	       | \
-	       :  (real size   :	       : |
-  EXT2 (CS3)   :   and content :	       :  > CONFIG_SYS_NIOS_CPU_CS2_SIZE
-	       :   unknown)    :	       : |   = 0x01000000
-	       |	       |	       | /
-  0x42000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_CS2_BASE
-	       |	       |	       | \
-	       :  (real size   :	       : |
-  EXT1 (CS2)   :   and content :	       :  > CONFIG_SYS_NIOS_CPU_CS1_SIZE
-	       :   unknown)    :	       : |   = 0x01000000
-	       |	       |	       | /
-  0x41000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_CS1_BASE
-	       |	       |	       | \
-	       :  (real size   :	       : |
-  EXT0 (CS1)   :   and content :	       :  > CONFIG_SYS_NIOS_CPU_CS0_SIZE
-	       :   unknown)    :	       : |   = 0x01000000
-	       |	       |	       | /
-  0x40000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_CS0_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -   external memory   - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x03000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_STACK
-	       |	       .	       | \
-	       |	       .	       | |  (U-Boot run-time system)
-	       |	       .	       | |
-	       |	       .	       |  > CONFIG_SYS_MONITOR_LEN
-	       |	       .	       | |   = 0x00040000
-	       |	       .	       | |
-	       |	       .	       | /
-  0x02fc0000 --+32-----------16|15------------0+    TEXT_BASE
-	       |	       .	       | \
-	       |	       .	       |  > CONFIG_SYS_MALLOC_LEN (heap)
-	       |	       .	       | /
-	     --+32-----------16|15------------0+
-	       |	       .	       | \
-	       |	       .	       |  > CONFIG_SYS_GBL_DATA_SIZE (global)
-	       |	       .	       | /
-	     --+32-----------16|15------------0+    CONFIG_SYS_INIT_SP (u-boot stack)
-	       |	       .	       | \ \
-	       |	       .	       | | |
-	       |	       .	       | |  > stack area
-	       |	       .	       | | |
-	       |	       .	       | | V
-	       |	       .	       | |
-	       |	       .	       | |
-  SDRAM	       |	       .	       |  > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
-	       |	       .	       | |   = 0x01000000
-	       |	       .	       | |
-  0x02000100   |- - - - - - - - - - - - - - - -+-|-
-	       |	       .	       | | \
-	       |	       .	       | | |
-	       |	       .	       | |  > CONFIG_SYS_NIOS_CPU_VEC_SIZE
-	       |	       .	       | | |   = 0x00000100
-	       |			       | / /
-  0x02000000   |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_VEC_BASE
-  0x02000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SDRAM_BASE
-	       |			       | \
-	       :	      gap	       :  > (space for 2nd Flash)
-	       |			       | /
-  0x01800000 ---32-----------16|15------------0-
-	       |  sector 127		       | \
-    + 0x7f0000 |- - - - - - - - - - - - - - - -| |
-	       |	       :	       | |
-  Flash	       |-   -	-   -  :  -   -	  -   -|  > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
-	       |  sector 1     :	       | |   = 0x00800000
-    + 0x010000 |- - - - - - - - - - - - - - - -| |
-	       |  sector 0 (size = 0x10000)    | /
-  0x01000000 ---8-------------4|3-------------0-    CONFIG_SYS_NIOS_CPU_FLASH_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -	 external i/o	  - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x00010020 ---32-----------16|15------------0-
-	       |			       | \
-	       |  register bank		       | |
-	       |   size = (real_size << 1)     | |
-	       |   real_size = 0x10	       | |
-	       | +--------.---.---.---	       | |
-	       | | bank 0 \ 1 \ 2 \ 3 \	       | |
-	       | |---------------------------+ | |
-  LAN91C111    | | BANK	       | RESERVED    | |  > na_enet_size
-	       | |- - - - - - -|- - - - - - -| | |   = 0x00000020
-	       | | RPCR	       | MIR	     | | |
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | COUNTER     | RCR	     | | |
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | EPH STATUS  | TCR	     | | |
-	       | +---------------------------+ | /
-  0x00010000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_LAN0_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x00001040 ---32-----------16|15------------0-
-	       |	       |	       | \
-	       :	       :	       : |
-  IDE1 i/f     :	       :	       :  > 0x00000020
-  [5]	       :	       :	       : |
-	       |	       |	       | /
-  0x00001020 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_IDE1
-	       |	       |	       | \
-	       :	       :	       : |
-  IDE0 i/f     :	       :	       :  > 0x00000020
-  [5]	       :	       :	       : |
-	       |	       |	       | /
-  0x00001000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_IDE0
-	       |			       |
-	       :	      gap	       :
-	       |			       |
-  0x00000980 ---32-----------16|15------------0-
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO13        |  interruptmask (1 bit)	 (rw)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x00000970 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO13
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO12        |  interruptmask (1 bit)	 (rw)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x00000960 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO12
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO11        |  interruptmask (1 bit)	 (rw)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x00000950 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO11
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO10        |  interruptmask (1 bit)	 (rw)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x00000940 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO10
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO9         |  interruptmask (1 bit)	 (rw)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x00000930 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO9
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO8         |  interruptmask (1 bit)	 (rw)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x00000920 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO8
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO7         |  interruptmask (1 bit)	 (rw)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x00000910 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO7
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO6         |  interruptmask (1 bit)	 (rw)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x00000900 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO6
-	       |			       |
-	       :	      gap	       :
-	       |			       |
-  0x000008e0 ---32-----------16|15------------0-
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |  endofpacket (16 bit)	 (rw)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |  slaveselect (1 bit)	 (rw)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  SPI0	       |		   (reserved)  | |
-  [4]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |  control (11 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (9 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (16 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (16 bit)	 (ro)  | /
-  0x000008c0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SPI0
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO5	       |		     (unused)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (wo)  | /
-  0x000008b0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO5
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO4	       |		     (unused)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (wo)  | /
-  0x000008a0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO4
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO3	       |		     (unused)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x00000890 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO3
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO2	       |		     (unused)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (4 bit)      (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (4 bit)		 (rw)  | /
-  0x00000880 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO2
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO1	       |		     (unused)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (8 bit)      (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (8 bit)		 (rw)  | /
-  0x00000870 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO1
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO0	       |		     (unused)  | |
-  [3]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (8 bit)      (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (8 bit)		 (rw)  | /
-  0x00000860 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |  snaph (16 bit)	 (rw)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  TIMER0       |  snapl (16 bit)	 (rw)  | |
-  [2]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |  periodh (16 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  periodl (16 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  control (4 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  status (2 bit)	 (rw)  | /
-  0x00000840 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART1	       |		     (unused)  |  > 0x00000020
-  [1]	+ 0x10 |- - - - - - - - - - - - - - - -| |
-	       |  control (10 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (10 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (8 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (8 bit)	 (ro)  | /
-  0x00000820 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART1
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART0	       |		     (unused)  |  > 0x00000020
-  [1]	+ 0x10 |- - - - - - - - - - - - - - - -| |
-	       |  control (10 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (10 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (8 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (8 bit)	 (ro)  | /
-  0x00000800 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART0
-
-- - - - - - - - - - -  on chip memory 1	  - - - - - - - - - - -
-
-  0x00000800 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  GERMS	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_ROM_SIZE
-	       |	       :	       | |   = 0x00000800
-	       |	       :	       | /
-  0x00000000   |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
-  0x00000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_ROM_BASE
-
-
-===============================================================================
-	F L A S H   M E M O R Y	  A L L O C A T I O N
-===============================================================================
-
-  0x01800000 ---8-------------4|3-------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-	       |	       :	       |  > 6 MByte ROM FS
-	       |	       :	       | |
-	       |	       :	       | /
-  0x01200000 --+- - - - - - - -:- - - - - - - -+- - file system image(s)
-	       |	       :	       | \
-	       |	       :	       | |
-	       |	       :	       |  > 1728 kByte ucLinux
-	       |	       :	       | |
-	       |	       :	       | /
-  0x01050000 --+- - - - - - - -:- - - - - - - -+- - os image(s)
-	       |	       :	       | \
-  0x01040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment
-	       |	       :	       | |
-	       |	       :	       |  > 320 kByte U-Boot
-	       |	       :	       | |
-	       |	       :	       | |
-	       |	       :	       | /
-  0x01000000 --+- - - - - - - -:- - - - - - - -+- - u-boot _start()
-  0x01000000 ---8-------------4|3-------------0-
-
-
-===============================================================================
-	R E F E R E N C E S
-===============================================================================
-[1]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
-[2]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
-[3]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
-[4]	http://www.altera.com/literature/ds/ds_nios_spi.pdf
-[5]	http://www.t13.org/index.html
-
-
-===============================================================================
-Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.dk1c20 b/doc/README.dk1c20
deleted file mode 100644
index 3c0e41bf7d..0000000000
--- a/doc/README.dk1c20
+++ /dev/null
@@ -1,153 +0,0 @@
-
-			 Nios Development Kit
-			   Cyclone Editions
-
-		    Last Update: January 2, 2004
-====================================================================
-
-This file contains information regarding U-Boot and the Altera
-Nios Development Kit, Cyclone Edition (DK-1C20). For general Nios
-information see doc/README.nios.
-
-For those interested in contributing ... see HELP WANTED section
-in doc/README.nios.
-
-Contents:
-
-	1. Files
-	2. Memory Organization
-	3. Examples
-	4. Programming U-Boot into FLASH with GERMS
-	5. Active Serial Memory Interface (ASMI) Support
-
-====================================================================
-
-1. Files
-=========
-	board/altera/dk1c20/*
-	include/configs/DK1C20.h
-
-2. Memory Organization
-=======================
-
-	-The heap is placed below the monitor (U-Boot code).
-	-Global data is placed below the heap.
-	-The stack is placed below global data (&grows down).
-
-3. Examples
-============
-
-The hello_world example works fine. The default load address
-is 0x0100_0000 (the start of SDRAM).
-
-
-4. Programming U-Boot into FLASH with GERMS
-============================================
-The current version of the DK-1C20 port with the default
-configuration settings occupies about 81 KBytes of flash.
-A minimal configuration occupies less than 60 KByte (asmi
-and network support disabled).
-
-To program U-Boot into the DK-1C20 flash using GERMS do the
-following:
-
-1. From the command line, download U-Boot using the nios-run:
-
-	$ nios-run -r u-boot.srec
-
-This takes about 45 seconds (GERMS is not very speedy here).
-After u-boot is downloaded it will be executed. You should
-see the following:
-
-    U-Boot 1.0.0-pre (Oct  4 2003 - 07:39:24)
-
-    CPU: Nios-32 Rev. 3.3 (0x3038)
-    Reg file size: 256 LO_LIMIT/HI_LIMIT: 2/14
-    Board: Altera Nios 1C20 Development Kit
-    In:	   serial
-    Out:   serial
-    Err:   serial
-    ==>
-
-
-2. Quit nios-run and start your terminal application (e.g. start
-Hyperterminal or minicom).
-
-3. Download the u-boot code to RAM. When using Hyperterminal, do the
-following:
-
-   a.  From the u-boot command prompt start a binary download to SRAM:
-
-    ==> loadb 800000
-
-    b. Download u-boot.bin using kermit.
-
-4. From the U-Boot command prompt, erase flash 0x40000 to 0x5ffff:
-
-    ==> erase 1:4-5
-
-5. Copy the binary image from SRAM to flash:
-
-    ==> cp.b 800000 40000 10000
-
-U-Boot will now automatically start when the board is powered on or
-reset using the Standard-32 configuration. To start U-Boot with the
-Safe-32 configuration, enter the following GERMS command:
-
-    + g 40000
-
-5. Active Serial Memory Interface (ASMI) Support
-================================================
-ASMI is fully supported in U-Boot. Please note that ASMI is supported
-only on Cyclone devices. Do not expect ASMI to work with Stratix or
-APEX devices.
-
-		 ************* IMPORTANT *************
-	 ===================================================
-	IN ORDER FOR THE NIOS ASMI TO OPERATE PROPERLY, THE
-	CYCLONE DEVICE MUST BE CONFIGURED USING JTAG OR ASMI.
-
-There are two techniques you can use to bootstrap the ASMI. The
-first is to use the program_epcs utility that is part of Altera's SDK.
-But I've found program_epcs to be slow and cumbersome at best.
-
-An undocumented alternative is to use the Quartus device programing
-interface:
-
-    1. Select "Active Serial" mode.
-
-    2. Choose the xxx.pof file. For example, for the standard_32
-       configuration use the "standard_32.pof" file.
-
-    3. Attach your ByteBlaster to J28. Make sure you have the
-       cable attached properly -- the orientation of J28 is
-       different than J24 (the JTAG header). On J28, pin 1 is on
-       the bottom row, left-most pin.
-
-    4. Press and hold the "Power-On Reset" switch (SW10). You will
-       see the green "Loading" and red "Error" LEDs (LED3 and LED4)
-       in the on state.
-
-    5. While holding down the "Power-On Reset" switch, start the
-       programming sequence. This only takes about 10 seconds.
-
-    6. After programming is complete, release the "Power-On Reset"
-       switch. The Cyclone device should now load its configuration
-       from the EPCS4 (U59). The green "User" LED (LED 1) should be
-       blinking if the device was successfully loaded via ASMI.
-
-    7. Remove the ByteBlaster cable. The cable must be removed to
-       allow the Nios ASMI access to the EPCS4 device.
-
-After you have successfully programmed a configuration into the
-EPCS4, the ASMI will be used to load the Cyclone configuration
-unless the "Force Safe" switch (SW9) is pressed.
-
-NOTE: To maximize the amount of space available for program use,
-you can enable configuration compression in Quartus. With compression
-enabled, the size of the standard_32 configuration data is
-approximately 192 KBytes.
-
-To use the U-Boot ASMI commands, try typing "help asmi" at the
-command prompt. The command "asmi info" will show the current
-status of the ASMI.
diff --git a/doc/README.dk1c20_std32 b/doc/README.dk1c20_std32
deleted file mode 100644
index 2be12998d3..0000000000
--- a/doc/README.dk1c20_std32
+++ /dev/null
@@ -1,366 +0,0 @@
-
-TODO:	specify IDE i/f
-	specify ASMI i/f
-	specify OCI
-
-
-===============================================================================
-	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
-===============================================================================
-see also [1]-[6]
-
-CPU:	"standard_32"
-	32 bit NIOS for 50 MHz
-	256 Byte for register file (15 levels)
-	4 KByte instruction cache (2 bytes in each cache line)
-	4 KByte data cache (4 bytes in each cache line)
-	2 KByte On Chip ROM with GERMS boot monitor
-	no On Chip RAM
-	MSTEP multiplier
-	no Debug Core
-	On Chip Instrumentation (OCI) enabled
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_CLK	     = 50000000
-			CONFIG_SYS_NIOS_CPU_ICACHE	     = 4096
-			CONFIG_SYS_NIOS_CPU_DCACHE	     = 4096
-			CONFIG_SYS_NIOS_CPU_REG_NUMS	     = 256
-			CONFIG_SYS_NIOS_CPU_MUL	     = 0
-			CONFIG_SYS_NIOS_CPU_MSTEP	     = 1
-			CONFIG_SYS_NIOS_CPU_DBG_CORE	     = 0
-
-OCI:	(TODO)
-
-IRQ:	 Nr.  | used by
-	------+--------------------------------------------------------
-	 16   | TIMER0	  |  CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
-	 25   | UART0	  |  CONFIG_SYS_NIOS_CPU_UART0_IRQ  = 25
-	 30   | LAN91C111 |  CONFIG_SYS_NIOS_CPU_LAN0_IRQ   = 30
-	 35   | PIO5	  |  CONFIG_SYS_NIOS_CPU_PIO5_IRQ   = 35
-	 40   | PIO0	  |  CONFIG_SYS_NIOS_CPU_PIO0_IRQ   = 40
-	 45   | ASMI	  |  CONFIG_SYS_NIOS_CPU_ASMI0_IRQ  = 45
-	 50   | TIMER1	  |  CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50
-
-MEMORY:	 8 MByte Flash
-	 1 MByte SRAM
-	16 MByte SDRAM
-
-ASMI:	(TODO) <-- ASMI part is 4M bits
-
-Timer:	TIMER0: high priority programmable timer (IRQ16)
-	TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_TICK_TIMER	     = 1
-			CONFIG_SYS_NIOS_CPU_USER_TIMER	     = 0
-
-PIO:	 Nr.  | description
-	------+--------------------------------------------------------
-	 PIO0 | BUTTON:	    4 inputs for user push buttons (IRQ40)
-	 PIO1 | LCD:	   11 in/outputs for ASCII LCD
-	 PIO2 | LED:	    8 outputs for user LEDs
-	 PIO3 | SEVENSEG:  16 outputs for user seven segment display
-	 PIO4 | RECONF:	    1 in/output for . . . . . . . . . . . .
-	 PIO5 | CFPRESENT:  1 input for CF present event (IRQ35)
-	 PIO6 | CFPOWER:    1 output to controll CF power supply
-	 PIO7 | CFATASEL:   1 output to controll CF ATA card select
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_BUTTON_PIO	     = 0
-			CONFIG_SYS_NIOS_CPU_LCD_PIO	     = 1
-			CONFIG_SYS_NIOS_CPU_LED_PIO	     = 2
-			CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO    = 3
-			CONFIG_SYS_NIOS_CPU_RECONF_PIO	     = 4
-			CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO   = 5
-			CONFIG_SYS_NIOS_CPU_CFPOWER_PIO     = 6
-			CONFIG_SYS_NIOS_CPU_CFATASEL_PIO    = 7
-
-UART:	UART0: fixed baudrate of 115200, fixed protocol 8N1,
-	       without handshake RTS/CTS (IRQ25)
-
-LAN:	SMsC LAN91C111 with:
-	  - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
-	  - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
-
-IDE:	(TODO)
-
-
-===============================================================================
-	M E M O R Y   M A P
-===============================================================================
-
-- - - - - - - - - - -  external memory 2  - - - - - - - - - - - - - - - - - - -
-
-  0x02000000 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  SDRAM	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
-	       |	       :	       | |   = 0x01000000
-	       |	       :	       | /
-  0x01000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SDRAM_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x________ ---32-----------16|15------------0-
-	       |	       |	       | \
-	       :  (real size   :	       : |
-  ASMI i/f     :   and content :	       :  > 0x________
-  [5]	       :   unknown)    :	       : |
-	       |	       |	       | /
-  0x00920b00 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_ASMI0
-	       |			       |
-	       :	      gap	       :
-	       |			       |
-  0x00920a80 ---32-----------16|15------------0-
-	       |	       |	       | \
-	       :  (real size   :	       : |
-  IDE i/f      :   and content :	       :  > 0x00000080
-  [6]	       :   unknown)    :	       : |
-	       |	       |	       | /
-  0x00920a00 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_IDE0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  TIMER1       |		     (unused)  | |
-  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |		     (unused)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  control (1 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  status (2 bit)	 (rw)  | /
-  0x009209e0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER1
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO7	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (wo)  | /
-  0x009209d0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO7
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO6	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (wo)  | /
-  0x009209c0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO6
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO5	       |  interruptmask (1 bit)	 (rw)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x009209b0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO5
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO4	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (1 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (rw)  | /
-  0x009209a0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO4
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO3	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (16 bit)		 (wo)  | /
-  0x00920990 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO3
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO2	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (8 bit)		 (wo)  | /
-  0x00920980 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO2
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO1	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (11 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (11 bit)		 (rw)  | /
-  0x00920970 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO1
-	       |  edgecapture (4 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO0	       |  interruptmask (4 bit)	 (rw)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (4 bit)		 (ro)  | /
-  0x00920960 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |  snaph (16 bit)	 (rw)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  TIMER0       |  snapl (16 bit)	 (rw)  | |
-  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |  periodh (16 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  periodl (16 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  control (4 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  status (2 bit)	 (rw)  | /
-  0x00920940 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER0
-	       |			       | \
-	       :	      gap	       :  > (space for UART1)
-	       |			       | /
-  0x00920920 ---32-----------16|15------------0-
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART0	       |		     (unused)  |  > 0x00000020
-  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
-	       |  control (10 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (10 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (8 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (8 bit)	 (ro)  | /
-  0x00920900 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART0
-
-- - - - - - - - - - -  on chip debugging  - - - - - - - - - - - - - - - - - - -
-
-  0x00920900 -----------------------------------
-	       |			       | \
-	       :  (real size		       : |
-  OCI Debug    :   and content		       :  > CONFIG_SYS_NIOS_CPU_OCI_SIZE
-	       :   unknown)		       : |   = 0x00000100
-	       |			       | /
-  0x00920800 -----------------------------------    CONFIG_SYS_NIOS_CPU_OCI_BASE
-
-- - - - - - - - - - -	on chip memory	  - - - - - - - - - - -
-
-  0x00920800 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  GERMS	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_ROM_SIZE
-	       |	       :	       | |   = 0x00000800
-	       |	       :	       | /
-  0x00920000   |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
-  0x00920000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_ROM_BASE
-
-- - - - - - - - - - -	 external i/o	  - - - - - - - - - - - - - - - - - - -
-
-  0x00920000 ---32-----------16|15------------0-
-	       |	      gap	       | \
-  0x00910310 --+-------------------------------| |
-	       |			       | |
-	       |  register bank (size = 0x10)  | |
-	       | +--------.---.---.---	       | |
-	       | | bank 0 \ 1 \ 2 \ 3 \	       | |
-	       | |---------------------------+ | |
-  LAN91C111    | | BANK	       | RESERVED    | | |
-	       | |- - - - - - -|- - - - - - -| |  > na_lan91c111_size
-	       | | RPCR	       | MIR	     | | |   = 0x00010000
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | COUNTER     | RCR	     | | |
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | EPH STATUS  | TCR	     | | |
-	       | +---------------------------+ | |
-  0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
-	       |	      gap	       | /
-  0x00910000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_LAN0_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -  external memory 1  - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x00900000 ---32-----------16|15------------0-
-  0x00900000 --+32-----------16|15------------0+
-	       |	       :	       | \ \
-	       |	       :	       | | |
-	       |	       :	       | |  > CONFIG_SYS_NIOS_CPU_VEC_SIZE
-	       |	       :	       | | |   = 0x00000100
-	       |	       :	       | | /
-  0x008fff00   |- - - - - - - -:- - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE
-  0x008fff00   |- - - - - - - -:- - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK
-	       |	       :	       | | \
-	       |	       :	       | | |
-	       |	       :	       | |  > stack area
-	       |	       :	       | | |
-	       |	       :	       | | V
-	       |	       :	       | |
-  SRAM	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
-	       |	       :	       | |   = 0x00100000
-	       |	       :	       | /
-  0x00800000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SRAM_BASE
-  0x00800000 ---8-------------4|3-------------0-
-	       |  sector 127		       | \
-    + 0x7f0000 |- - - - - - - - - - - - - - - -| |
-	       |	       :	       | |
-  Flash	       |-   -	-   -  :  -   -	  -   -|  > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
-	       |  sector 1     :	       | |   = 0x00800000
-    + 0x010000 |- - - - - - - - - - - - - - - -| |
-	       |  sector 0 (size = 0x10000)    | /
-  0x00000000 ---8-------------4|3-------------0-    CONFIG_SYS_NIOS_CPU_FLASH_BASE
-
-
-===============================================================================
-	F L A S H   M E M O R Y	  A L L O C A T I O N
-===============================================================================
-
-  0x00800000 ---8-------------4|3-------------0-
-	       |	       :	       | \
-  SAFE	       |	       :	       |  > 1 MByte
-  FPGA conf.   |	       :	       | /    (NOT usable by software)
-  0x00700000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-  USER	       |	       :	       |  > 1 MByte
-  FPGA conf.   |	       :	       | /    (NOT usable by software)
-  0x00600000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-  WEB pages    |	       :	       |  > 2 MByte
-	       |	       :	       | |    (provisory usable)
-	       |	       :	       | /
-  0x00400000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-	       |	       :	       | |
-	       |	       :	       |  > 4 MByte free for use
-	       |	       :	       | |
-  0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
-	       |	       :	       | /
-  0x00000000   |- - - - - - - -:- - - - - - - -+- - u-boot environment
-  0x00000000 ---8-------------4|3-------------0-
-
-
-===============================================================================
-	R E F E R E N C E S
-===============================================================================
-[1]	http://www.altera.com/literature/manual/mnl_nios_board_cyclone_1c20.pdf
-[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
-[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
-[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
-[5]	http://www.altera.com/literature/ds/ds_nios_asmi.pdf
-	http://www.altera.com/literature/wp/wp_epcs_cyc.pdf
-[6]	http://www.opencores.org/projects/ata/
-	http://www.t13.org/index.html
-
-
-===============================================================================
-Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.dk1s10 b/doc/README.dk1s10
deleted file mode 100644
index 622bef5374..0000000000
--- a/doc/README.dk1s10
+++ /dev/null
@@ -1,131 +0,0 @@
-
-			 Nios Development Kit
-			   Startix Editions
-
-		    Last Update: January 28, 2004
-====================================================================
-
-This file contains information regarding U-Boot and the Altera
-Nios Development Kit, Startix Edition (DK-1S10). For general Nios
-information see doc/README.nios.
-
-Most stuff of this file was borrowed and based on README.dk1c20,
-the DK-1C20 related information file.
-
-For those interested in contributing ... see HELP WANTED section
-in doc/README.nios.
-
-Contents:
-
-	1. Files
-	2. Memory Organization
-	3. CPU Variations
-	4. Examples
-	5. Programming U-Boot into FLASH with GERMS
-
-====================================================================
-
-1. Files
-=========
-	board/altera/dk1s10/*
-	include/configs/DK1S10.h
-
-2. Memory Organization
-=======================
-
-	-The heap is placed below the monitor (U-Boot code).
-	-Global data is placed below the heap.
-	-The stack is placed below global data (&grows down).
-
-3. CPU Variations
-=================
-
-There are more than one NIOS CPU variation for the DK-1S10. U-Boot
-supports the following CPU configurations:
-
-	- Altera Standard 32 (make DK1S10_standard_32_config)
-	- Microtronix LDK 2.0 (make DK1S10_mtx_ldk_20_config)
-
-4. Examples
-============
-
-The hello_world example was never tested on DK-1S10. Neverthelse
-it should work as far as possible, because the DK-1S10 port is
-more than ninetieth percents equal to the DK-1C20 port and at
-this platform the hello_world example was already tested
-successfully (see README.dk1c20).
-
-
-5. Programming U-Boot into FLASH with GERMS
-============================================
-The current version of the DK-1S10 port with the default
-configuration settings occupies about 78 KBytes of flash.
-A minimal configuration occupies less than 60 KByte
-(network support disabled).
-
-To program U-Boot into the DK-1S10 flash using GERMS do the
-following:
-
-1. From the command line, download U-Boot using the nios-run:
-
-	$ nios-run -r u-boot.srec
-
-This takes about 45 seconds (GERMS is not very speedy here).
-After u-boot is downloaded it will be executed. You should
-see the following:
-
-    U-Boot 1.0.2 (Jan 28 2004 - 19:02:30)
-
-    CPU: Nios-32 Rev. 3.3 (0x3038)
-    Reg file size: 256 LO_LIMIT/HI_LIMIT: 2/14
-    Board: Altera Nios 1S10 Development Kit
-    In:    serial
-    Out:   serial
-    Err:   serial
-    DK1S10 >
-
-
-2. Quit nios-run and start your terminal application (e.g. start
-   Hyperterminal or minicom).
-
-3. Download the u-boot code to RAM. When using Hyperterminal, do the
-   following:
-
-   a. From the u-boot command prompt start a binary download to
-      SRAM / SDRAM:
-
-      at the Altera Standard 32 to SRAM:
-
-	==> loadb 800000
-
-      at the Microtronix LDK 2.0 to SDRAM:
-
-	==> loadb 1010000
-
-   b. Download u-boot.bin using kermit.
-
-4. From the U-Boot command prompt, erase flash:
-
-   at the Altera Standard 32 from 0x40000 to 0x5ffff:
-
-	==> erase 1:4-5
-
-   at the Microtronix LDK 2.0 from 0x8000000 to 0x81ffff:
-
-	==> erase 1:0-1
-
-5. Copy the binary image from SRAM / SDRAM to flash:
-
-   at the Altera Standard 32 to SRAM:
-
-	==> cp.b 800000 40000 ${filesize}
-
-   at the Microtronix LDK 2.0 to SDRAM:
-
-	==> cp.b 1010000 8000000 ${filesize}
-
-U-Boot will now automatically start when the board is powered on or
-reset using the Standard-32 configuration. To start U-Boot with the
-Safe-32 configuration, enter the following GERMS command:
-
-    + g 40000
diff --git a/doc/README.dk1s10_mldk20 b/doc/README.dk1s10_mldk20
deleted file mode 100644
index 74e07a93d1..0000000000
--- a/doc/README.dk1s10_mldk20
+++ /dev/null
@@ -1,286 +0,0 @@
-
-TODO:	specify IDE i/f
-
-
-===============================================================================
-	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
-===============================================================================
-see also [1]-[5]
-
-CPU:	"LDK2"
-	32 bit NIOS for 75 MHz
-	512 Byte for register file (30 levels)
-	with out instruction cache
-	with out data cache
-	2 KByte On Chip ROM with GERMS boot monitor
-	with out On Chip RAM
-	MSTEP multiplier
-	no Debug Core
-	no On Chip Instrumentation (OCI)
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_CLK	     = 75000000
-			CONFIG_SYS_NIOS_CPU_ICACHE	     = (not present)
-			CONFIG_SYS_NIOS_CPU_DCACHE	     = (not present)
-			CONFIG_SYS_NIOS_CPU_REG_NUMS	     = 512
-			CONFIG_SYS_NIOS_CPU_MUL	     = 0
-			CONFIG_SYS_NIOS_CPU_MSTEP	     = 1
-			CONFIG_SYS_NIOS_CPU_DBG_CORE	     = 0
-
-IRQ:	 Nr.  | used by
-	------+--------------------------------------------------------
-	 16   | TIMER0	  |  CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
-	 17   | UART0	  |  CONFIG_SYS_NIOS_CPU_UART0_IRQ  = 17
-	 18   | UART1	  |  CONFIG_SYS_NIOS_CPU_UART1_IRQ  = 18
-	 20   | LAN91C111 |  CONFIG_SYS_NIOS_CPU_LAN0_IRQ   = 20
-	 25   | IDE0	  |  CONFIG_SYS_NIOS_CPU_IDE0_IRQ   = 25
-
-MEMORY:	 8 MByte Flash
-	16 MByte SDRAM
-
-Timer:	TIMER0: high priority programmable timer (IRQ16)
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_TICK_TIMER	     = 0
-			CONFIG_SYS_NIOS_CPU_USER_TIMER	     = (not present)
-
-PIO:	 Nr.  | description
-	------+--------------------------------------------------------
-	 PIO0 | CFPOWER:    1 output to controll CF power supply
-	 PIO1 | BUTTON:	    4 inputs for user push buttons (no IRQ)
-	------+--------------------------------------------------------
-	 not  | LCD:	   11 in/outputs for ASCII LCD
-	 pres.| LED:	    8 outputs for user LEDs
-	      | SEVENSEG:  16 outputs for user seven segment display
-	      | RECONF:	    1 in/output for . . . . . . . . . . . .
-	      | CFPRESENT:  1 input for CF present event (IRQ35)
-	      | CFATASEL:   1 output to controll CF ATA card select
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_BUTTON_PIO	     = 1
-			CONFIG_SYS_NIOS_CPU_LCD_PIO	     = (not present)
-			CONFIG_SYS_NIOS_CPU_LED_PIO	     = (not present)
-			CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO    = (not present)
-			CONFIG_SYS_NIOS_CPU_RECONF_PIO	     = (not present)
-			CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO   = (not present)
-			CONFIG_SYS_NIOS_CPU_CFPOWER_PIO     = 0
-			CONFIG_SYS_NIOS_CPU_CFATASEL_PIO    = (not present)
-
-UART:	UART0: fixed baudrate of 115200, fixed protocol 8N2,
-	       without handshake RTS/CTS (IRQ17)
-	UART1: fixed baudrate of 115200, fixed protocol 8N1,
-	       without handshake RTS/CTS (IRQ18)
-
-LAN:	SMsC LAN91C111 with:
-	  - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
-	  - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
-
-IDE:	(TODO)
-
-
-===============================================================================
-	M E M O R Y   M A P
-===============================================================================
-
-- - - - - - - - - - -   external memory   - - - - - - - - - - - - - - - - - - -
-
-  0x02000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_STACK
-  0x02000000 --+32-----------16|15------------0+
-	       |	       .	       | \ \
-	       |	       .	       | | |
-	       |	       .	       | |  > stack area
-	       |	       .	       | | |
-	       |	       .	       | | V
-	       |	       .	       | |
-	       |	       .	       | |
-  SDRAM	       |	       .	       |  > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
-	       |	       .	       | |   = 0x01000000
-	       |	       .	       | |
-  0x01000100   |- - - - - - - - - - - - - - - -+-|-
-	       |	       .	       | | \
-	       |	       .	       | | |
-	       |	       .	       | |  > CONFIG_SYS_NIOS_CPU_VEC_SIZE
-	       |	       .	       | | |   = 0x00000100
-	       |			       | / /
-  0x01000000   |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_VEC_BASE
-  0x01000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SDRAM_BASE
-	       |  sector 127		       | \
-    + 0x7f0000 |- - - - - - - - - - - - - - - -| |
-	       |	       :	       | |
-  Flash	       |-   -	-   -  :  -   -	  -   -|  > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
-	       |  sector 1     :	       | |   = 0x00800000
-    + 0x010000 |- - - - - - - - - - - - - - - -| |
-	       |  sector 0 (size = 0x10000)    | /
-  0x00800000 ---8-------------4|3-------------0-    CONFIG_SYS_NIOS_CPU_FLASH_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -	 external i/o	  - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x00020000 ---32-----------16|15------------0-
-	       |	      gap	       | \
-  0x00010310 --+-------------------------------| |
-	       |			       | |
-	       |  register bank (size = 0x10)  | |
-	       | +--------.---.---.---	       | |
-	       | | bank 0 \ 1 \ 2 \ 3 \	       | |
-	       | |---------------------------+ | |
-  LAN91C111    | | BANK	       | RESERVED    | | |
-	       | |- - - - - - -|- - - - - - -| |  > na_enet_size
-	       | | RPCR	       | MIR	     | | |   = 0x00010000
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | COUNTER     | RCR	     | | |
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | EPH STATUS  | TCR	     | | |
-	       | +---------------------------+ | |
-  0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| |
-	       |	      gap	       | /
-  0x00010000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_LAN0_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x00000980 ---32-----------16|15------------0-
-	       |	       |	       | \
-	       :  (real size   :	       : |
-  IDE i/f      :   and content :	       :  > 0x00000080
-  [5]	       :   unknown)    :	       : |
-	       |	       |	       | /
-  0x00000900 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_IDE0
-	       |			       | \
-	       :	      gap	       :  > (space for PIO4..7)
-	       |			       | /
-  0x000008c0 ---32-----------16|15------------0-
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART1	       |		     (unused)  |  > 0x00000020
-  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
-	       |  control (10 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (10 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (8 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (8 bit)	 (ro)  | /
-  0x000008a0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART1
-	       |			       | \
-	       :	      gap	       :  > (space for PIO2..3)
-	       |			       | /
-  0x00000880 ---32-----------16|15------------0-
-	       |  edgecapture (4 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO1	       |  interruptmask (4 bit)	 (rw)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (4 bit)		 (ro)  | /
-  0x00000870 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO1
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO0	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (wo)  | /
-  0x00000860 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |  snaph (16 bit)	 (rw)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  TIMER0       |  snapl (16 bit)	 (rw)  | |
-  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |  periodh (16 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  periodl (16 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  control (4 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  status (2 bit)	 (rw)  | /
-  0x00000840 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER0
-	       |			       | \
-	       :	      gap	       :  > (space for UART2)
-	       |			       | /
-  0x00000820 ---32-----------16|15------------0-
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART0	       |		     (unused)  |  > 0x00000020
-  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
-	       |  control (10 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (10 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (8 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (8 bit)	 (ro)  | /
-  0x00000800 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART0
-
-- - - - - - - - - - -  on chip memory 1	  - - - - - - - - - - -
-
-  0x00000800 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  GERMS	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_ROM_SIZE
-	       |	       :	       | |   = 0x00000800
-	       |	       :	       | /
-  0x00000000   |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
-  0x00000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_ROM_BASE
-
-===============================================================================
-	F L A S H   M E M O R Y	  A L L O C A T I O N
-===============================================================================
-
-  0x01000000 ---8-------------4|3-------------0-
-	       |	       :	       | \
-  SAFE	       |	       :	       |  > 1 MByte
-  FPGA conf.   |	       :	       | /    (NOT usable by software)
-  0x00f00000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-  USER	       |	       :	       |  > 1 MByte
-  FPGA conf.   |	       :	       | /    (NOT usable by software)
-  0x00e00000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-  WEB pages    |	       :	       |  > 2 MByte
-	       |	       :	       | |    (provisory usable)
-	       |	       :	       | /
-  0x00c00000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-	       |	       :	       | |
-	       |	       :	       |  > 4 MByte free for use
-	       |	       :	       | |
-  0x00840000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment
-	       |	       :	       | /
-  0x00800000   |- - - - - - - -:- - - - - - - -+- - u-boot _start()
-  0x00800000 ---8-------------4|3-------------0-
-
-
-===============================================================================
-	R E F E R E N C E S
-===============================================================================
-[1]	http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf
-[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
-[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
-[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
-[5]	http://www.opencores.org/projects/ata/
-	http://www.t13.org/index.html
-
-
-===============================================================================
-Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.dk1s10_std32 b/doc/README.dk1s10_std32
deleted file mode 100644
index 622b2b9c83..0000000000
--- a/doc/README.dk1s10_std32
+++ /dev/null
@@ -1,354 +0,0 @@
-
-TODO:	specify IDE i/f
-	specify OCI
-
-
-===============================================================================
-	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
-===============================================================================
-see also [1]-[5]
-
-CPU:	"standard_32"
-	32 bit NIOS for 50 MHz
-	256 Byte for register file (15 levels)
-	4 KByte instruction cache (4 bytes in each cache line)
-	4 KByte data cache (4 bytes in each cache line)
-	2 KByte On Chip ROM with GERMS boot monitor
-	64 KByte On Chip RAM
-	MSTEP multiplier
-	no Debug Core
-	On Chip Instrumentation (OCI) enabled
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_CLK	     = 50000000
-			CONFIG_SYS_NIOS_CPU_ICACHE	     = 4096
-			CONFIG_SYS_NIOS_CPU_DCACHE	     = 4096
-			CONFIG_SYS_NIOS_CPU_REG_NUMS	     = 256
-			CONFIG_SYS_NIOS_CPU_MUL	     = 0
-			CONFIG_SYS_NIOS_CPU_MSTEP	     = 1
-			CONFIG_SYS_NIOS_CPU_DBG_CORE	     = 0
-
-OCI:	(TODO)
-
-IRQ:	 Nr.  | used by
-	------+--------------------------------------------------------
-	 16   | TIMER0	  |  CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
-	 25   | UART0	  |  CONFIG_SYS_NIOS_CPU_UART0_IRQ  = 25
-	 30   | LAN91C111 |  CONFIG_SYS_NIOS_CPU_LAN0_IRQ   = 30
-	 35   | PIO5	  |  CONFIG_SYS_NIOS_CPU_PIO5_IRQ   = 35
-	 40   | PIO0	  |  CONFIG_SYS_NIOS_CPU_PIO0_IRQ   = 40
-	 50   | TIMER1	  |  CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50
-
-MEMORY:	 8 MByte Flash
-	 1 MByte SRAM
-	16 MByte SDRAM
-
-Timer:	TIMER0: high priority programmable timer (IRQ16)
-	TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_TICK_TIMER	     = 1
-			CONFIG_SYS_NIOS_CPU_USER_TIMER	     = 0
-
-PIO:	 Nr.  | description
-	------+--------------------------------------------------------
-	 PIO0 | BUTTON:	    4 inputs for user push buttons (IRQ40)
-	 PIO1 | LCD:	   11 in/outputs for ASCII LCD
-	 PIO2 | LED:	    8 outputs for user LEDs
-	 PIO3 | SEVENSEG:  16 outputs for user seven segment display
-	 PIO4 | RECONF:	    1 in/output for . . . . . . . . . . . .
-	 PIO5 | CFPRESENT:  1 input for CF present event (IRQ35)
-	 PIO6 | CFPOWER:    1 output to controll CF power supply
-	 PIO7 | CFATASEL:   1 output to controll CF ATA card select
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_BUTTON_PIO	     = 0
-			CONFIG_SYS_NIOS_CPU_LCD_PIO	     = 1
-			CONFIG_SYS_NIOS_CPU_LED_PIO	     = 2
-			CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO    = 3
-			CONFIG_SYS_NIOS_CPU_RECONF_PIO	     = 4
-			CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO   = 5
-			CONFIG_SYS_NIOS_CPU_CFPOWER_PIO     = 6
-			CONFIG_SYS_NIOS_CPU_CFATASEL_PIO    = 7
-
-UART:	UART0: fixed baudrate of 115200, fixed protocol 8N1,
-	       without handshake RTS/CTS (IRQ25)
-
-LAN:	SMsC LAN91C111 with:
-	  - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
-	  - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
-
-IDE:	(TODO)
-
-
-===============================================================================
-	M E M O R Y   M A P
-===============================================================================
-
-- - - - - - - - - - -  external memory 2  - - - - - - - - - - - - - - - - - - -
-
-  0x02000000 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  SDRAM	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_SDRAM_SIZE
-	       |	       :	       | |   = 0x01000000
-	       |	       :	       | /
-  0x01000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SDRAM_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x00920a80 ---32-----------16|15------------0-
-	       |	       |	       | \
-	       :  (real size   :	       : |
-  IDE i/f      :   and content :	       :  > 0x00000080
-  [5]	       :   unknown)    :	       : |
-	       |	       |	       | /
-  0x00920a00 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_IDE0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  TIMER1       |		     (unused)  | |
-  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |		     (unused)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  control (1 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  status (2 bit)	 (rw)  | /
-  0x009209e0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER1
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO7	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (wo)  | /
-  0x009209d0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO7
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO6	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (wo)  | /
-  0x009209c0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO6
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO5	       |  interruptmask (1 bit)	 (rw)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x009209b0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO5
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO4	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (1 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (rw)  | /
-  0x009209a0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO4
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO3	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (16 bit)		 (wo)  | /
-  0x00920990 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO3
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO2	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (8 bit)		 (wo)  | /
-  0x00920980 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO2
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO1	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (11 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (11 bit)		 (rw)  | /
-  0x00920970 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO1
-	       |  edgecapture (4 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO0	       |  interruptmask (4 bit)	 (rw)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (4 bit)		 (ro)  | /
-  0x00920960 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |  snaph (16 bit)	 (rw)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  TIMER0       |  snapl (16 bit)	 (rw)  | |
-  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |  periodh (16 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  periodl (16 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  control (4 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  status (2 bit)	 (rw)  | /
-  0x00920940 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER0
-	       |			       | \
-	       :	      gap	       :  > (space for UART1)
-	       |			       | /
-  0x00920920 ---32-----------16|15------------0-
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART0	       |		     (unused)  |  > 0x00000020
-  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
-	       |  control (10 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (10 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (8 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (8 bit)	 (ro)  | /
-  0x00920900 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART0
-
-- - - - - - - - - - -  on chip debugging  - - - - - - - - - - - - - - - - - - -
-
-  0x00920900 -----------------------------------
-	       |			       | \
-	       :  (real size		       : |
-  OCI Debug    :   and content		       :  > CONFIG_SYS_NIOS_CPU_OCI_SIZE
-	       :   unknown)		       : |   = 0x00000100
-	       |			       | /
-  0x00920800 -----------------------------------    CONFIG_SYS_NIOS_CPU_OCI_BASE
-
-- - - - - - - - - - -  on chip memory 2	  - - - - - - - - - - -
-
-  0x00920800 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  GERMS	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_ROM_SIZE
-	       |	       :	       | |   = 0x00000800
-	       |	       :	       | /
-  0x00920000   |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
-  0x00920000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_ROM_BASE
-
-- - - - - - - - - - -	 external i/o	  - - - - - - - - - - - - - - - - - - -
-
-  0x00920000 ---32-----------16|15------------0-
-	       |	      gap	       | \
-  0x00910310 --+-------------------------------| |
-	       |			       | |
-	       |  register bank (size = 0x10)  | |
-	       | +--------.---.---.---	       | |
-	       | | bank 0 \ 1 \ 2 \ 3 \	       | |
-	       | |---------------------------+ | |
-  LAN91C111    | | BANK	       | RESERVED    | | |
-	       | |- - - - - - -|- - - - - - -| |  > na_lan91c111_size
-	       | | RPCR	       | MIR	     | | |   = 0x00010000
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | COUNTER     | RCR	     | | |
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | EPH STATUS  | TCR	     | | |
-	       | +---------------------------+ | |
-  0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
-	       |	      gap	       | /
-  0x00910000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_LAN0_BASE
-
-- - - - - - - - - - -  on chip memory 1	  - - - - - - - - - - -
-
-  0x00910000 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  onchip RAM   |	       :	       |  > CONFIG_SYS_NIOS_CPU_RAM_SIZE
-	       |	       :	       | |   = 0x00010000
-	       |	       :	       | /
-  0x00900000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_RAM_BASE
-
-- - - - - - - - - - -  external memory 1  - - - - - - - - - - - - - - - - - - -
-
-  0x00900000 ---32-----------16|15------------0-
-  0x00900000 --+32-----------16|15------------0+
-	       |	       .	       | \ \
-	       |	       .	       | | |
-	       |	       .	       | |  > CONFIG_SYS_NIOS_CPU_VEC_SIZE
-	       |	       .	       | | |   = 0x00000100
-	       |	       .	       | | /
-  0x008fff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE
-  0x008fff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK
-	       |	       .	       | | \
-	       |	       .	       | | |
-	       |	       .	       | |  > stack area
-	       |	       .	       | | |
-	       |	       .	       | | V
-	       |	       .	       | |
-  SRAM	       |	       .	       |  > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
-	       |	       .	       | |   = 0x00100000
-	       |			       | /
-  0x00800000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SRAM_BASE
-  0x00800000 ---8-------------4|3-------------0-
-	       |  sector 127		       | \
-    + 0x7f0000 |- - - - - - - - - - - - - - - -| |
-	       |	       :	       | |
-  Flash	       |-   -	-   -  :  -   -	  -   -|  > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
-	       |  sector 1     :	       | |   = 0x00800000
-    + 0x010000 |- - - - - - - - - - - - - - - -| |
-	       |  sector 0 (size = 0x10000)    | /
-  0x00000000 ---8-------------4|3-------------0-    CONFIG_SYS_NIOS_CPU_FLASH_BASE
-
-
-===============================================================================
-	F L A S H   M E M O R Y	  A L L O C A T I O N
-===============================================================================
-
-  0x00800000 ---8-------------4|3-------------0-
-	       |	       :	       | \
-  SAFE	       |	       :	       |  > 1 MByte
-  FPGA conf.   |	       :	       | /    (NOT usable by software)
-  0x00700000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-  USER	       |	       :	       |  > 1 MByte
-  FPGA conf.   |	       :	       | /    (NOT usable by software)
-  0x00600000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-  WEB pages    |	       :	       |  > 2 MByte
-	       |	       :	       | |    (provisory usable)
-	       |	       :	       | /
-  0x00400000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-	       |	       :	       | |
-	       |	       :	       |  > 4 MByte free for use
-	       |	       :	       | |
-  0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
-	       |	       :	       | /
-  0x00000000   |- - - - - - - -:- - - - - - - -+- - u-boot environment
-  0x00000000 ---8-------------4|3-------------0-
-
-
-===============================================================================
-	R E F E R E N C E S
-===============================================================================
-[1]	http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf
-[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
-[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
-[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
-[5]	http://www.opencores.org/projects/ata/
-	http://www.t13.org/index.html
-
-
-===============================================================================
-Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.dk1s40_std32 b/doc/README.dk1s40_std32
deleted file mode 100644
index 9a0ea060c7..0000000000
--- a/doc/README.dk1s40_std32
+++ /dev/null
@@ -1,355 +0,0 @@
-
-TODO:	specify IDE i/f
-	specify OCI
-
-
-===============================================================================
-	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
-===============================================================================
-see also [1]-[5]
-
-CPU:	"standard_32"
-	32 bit NIOS for 50 MHz
-	256 Byte for register file (15 levels)
-	4 KByte instruction cache (4 bytes in each cache line)
-	4 KByte data cache (4 bytes in each cache line)
-	2 KByte On Chip ROM with GERMS boot monitor
-	64 KByte On Chip RAM
-	MSTEP multiplier
-	no Debug Core
-	On Chip Instrumentation (OCI) enabled
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_CLK	     = 50000000
-			CONFIG_SYS_NIOS_CPU_ICACHE	     = 4096
-			CONFIG_SYS_NIOS_CPU_DCACHE	     = 4096
-			CONFIG_SYS_NIOS_CPU_REG_NUMS	     = 256
-			CONFIG_SYS_NIOS_CPU_MUL	     = 0
-			CONFIG_SYS_NIOS_CPU_MSTEP	     = 1
-			CONFIG_SYS_NIOS_CPU_DBG_CORE	     = 0
-
-OCI:	(TODO)
-
-IRQ:	 Nr.  | used by
-	------+--------------------------------------------------------
-	 16   | TIMER0	  |  CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 16
-	 25   | UART0	  |  CONFIG_SYS_NIOS_CPU_UART0_IRQ  = 25
-	 30   | LAN91C111 |  CONFIG_SYS_NIOS_CPU_LAN0_IRQ   = 30
-	 35   | PIO5	  |  CONFIG_SYS_NIOS_CPU_PIO5_IRQ   = 35
-	 40   | PIO0	  |  CONFIG_SYS_NIOS_CPU_PIO0_IRQ   = 40
-	 50   | TIMER1	  |  CONFIG_SYS_NIOS_CPU_TIMER1_IRQ = 50
-
-MEMORY:	 8 MByte Flash
-	 1 MByte SRAM
-	16 MByte SDRAM
-
-Timer:	TIMER0: high priority programmable timer (IRQ16)
-	TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_TICK_TIMER	     = 1
-			CONFIG_SYS_NIOS_CPU_USER_TIMER	     = 0
-
-PIO:	 Nr.  | description
-	------+--------------------------------------------------------
-	 PIO0 | BUTTON:	    4 inputs for user push buttons (IRQ40)
-	 PIO1 | LCD:	   11 in/outputs for ASCII LCD
-	 PIO2 | LED:	    8 outputs for user LEDs
-	 PIO3 | SEVENSEG:  16 outputs for user seven segment display
-	 PIO4 | RECONF:	    1 in/output for . . . . . . . . . . . .
-	 PIO5 | CFPRESENT:  1 input for CF present event (IRQ35)
-	 PIO6 | CFPOWER:    1 output to controll CF power supply
-	 PIO7 | CFATASEL:   1 output to controll CF ATA card select
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_BUTTON_PIO	     = 0
-			CONFIG_SYS_NIOS_CPU_LCD_PIO	     = 1
-			CONFIG_SYS_NIOS_CPU_LED_PIO	     = 2
-			CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO    = 3
-			CONFIG_SYS_NIOS_CPU_RECONF_PIO	     = 4
-			CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO   = 5
-			CONFIG_SYS_NIOS_CPU_CFPOWER_PIO     = 6
-			CONFIG_SYS_NIOS_CPU_CFATASEL_PIO    = 7
-
-UART:	UART0: fixed baudrate of 115200, fixed protocol 8N1,
-	       without handshake RTS/CTS (IRQ25)
-
-LAN:	SMsC LAN91C111 with:
-	  - offset 0x300 (LAN91C111_REGISTERS_OFFSET)
-	  - data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
-
-IDE:	(TODO)
-
-
-===============================================================================
-	M E M O R Y   M A P
-===============================================================================
-
-- - - - - - - - - - -  external memory 2  - - - - - - - - - - - - - - - - - - -
-
-  0x02000000 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  SDRAM	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
-	       |	       :	       | |   = 0x01000000
-	       |	       :	       | /
-  0x01000000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SRAM_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x00920a80 ---32-----------16|15------------0-
-	       |	       |	       | \
-	       :  (real size   :	       : |
-  IDE i/f      :   and content :	       :  > 0x00000080
-  [5]	       :   unknown)    :	       : |
-	       |	       |	       | /
-  0x00920a00 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_IDE0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  TIMER1       |		     (unused)  | |
-  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |		     (unused)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  control (1 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  status (2 bit)	 (rw)  | /
-  0x009209e0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER1
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO7	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (wo)  | /
-  0x009209d0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO7
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO6	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (wo)  | /
-  0x009209c0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO6
-	       |  edgecapture (1 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO5	       |  interruptmask (1 bit)	 (rw)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (ro)  | /
-  0x009209b0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO5
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO4	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (1 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (1 bit)		 (rw)  | /
-  0x009209a0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO4
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO3	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (16 bit)		 (wo)  | /
-  0x00920990 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO3
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO2	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (8 bit)		 (wo)  | /
-  0x00920980 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO2
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO1	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (11 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (11 bit)		 (rw)  | /
-  0x00920970 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO1
-	       |  edgecapture (4 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO0	       |  interruptmask (4 bit)	 (rw)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (4 bit)		 (ro)  | /
-  0x00920960 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |  snaph (16 bit)	 (rw)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  TIMER0       |  snapl (16 bit)	 (rw)  | |
-  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |  periodh (16 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  periodl (16 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  control (4 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  status (2 bit)	 (rw)  | /
-  0x00920940 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER0
-	       |			       | \
-	       :	      gap	       :  > (space for UART1)
-	       |			       | /
-  0x00920920 ---32-----------16|15------------0-
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART0	       |		     (unused)  |  > 0x00000020
-  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
-	       |  control (10 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (10 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (8 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (8 bit)	 (ro)  | /
-  0x00920900 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART0
-
-- - - - - - - - - - -  on chip debugging  - - - - - - - - - - - - - - - - - - -
-
-  0x00920900 -----------------------------------
-	       |			       | \
-	       :  (real size		       : |
-  OCI Debug    :   and content		       :  > CONFIG_SYS_NIOS_CPU_OCI_SIZE
-	       :   unknown)		       : |   = 0x00000100
-	       |			       | /
-  0x00920800 -----------------------------------    CONFIG_SYS_NIOS_CPU_OCI_BASE
-
-- - - - - - - - - - -  on chip memory 2	  - - - - - - - - - - -
-
-  0x00920800 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  GERMS	       |	       :	       |  > CONFIG_SYS_NIOS_CPU_ROM_SIZE
-	       |	       :	       | |   = 0x00000800
-	       |	       :	       | /
-  0x00920000   |- - - - - - - - - - - - - - - -+- - CONFIG_SYS_NIOS_CPU_RST_VECT
-  0x00920000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_ROM_BASE
-
-- - - - - - - - - - -	 external i/o	  - - - - - - - - - - - - - - - - - - -
-
-  0x00920000 ---32-----------16|15------------0-
-	       |	      gap	       | \
-  0x00910310 --+-------------------------------| |
-	       |			       | |
-	       |  register bank (size = 0x10)  | |
-	       | +--------.---.---.---	       | |
-	       | | bank 0 \ 1 \ 2 \ 3 \	       | |
-	       | |---------------------------+ | |
-  LAN91C111    | | BANK	       | RESERVED    | | |
-	       | |- - - - - - -|- - - - - - -| |  > na_lan91c111_size
-	       | | RPCR	       | MIR	     | | |   = 0x00010000
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | COUNTER     | RCR	     | | |
-	       | |- - - - - - -|- - - - - - -| | |
-	       | | EPH STATUS  | TCR	     | | |
-	       | +---------------------------+ | |
-  0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
-	       |	      gap	       | /
-  0x00910000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_LAN0_BASE
-
-- - - - - - - - - - -  on chip memory 1	  - - - - - - - - - - -
-
-  0x00910000 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  onchip RAM   |	       :	       |  > CONFIG_SYS_NIOS_CPU_RAM_SIZE
-	       |	       :	       | |   = 0x00010000
-	       |	       :	       | /
-  0x00900000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_RAM_BASE
-
-- - - - - - - - - - -  external memory 1  - - - - - - - - - - - - - - - - - - -
-
-  0x00900000 ---32-----------16|15------------0-
-  0x00900000 --+32-----------16|15------------0+
-	       |	       .	       | \ \
-	       |	       .	       | | |
-	       |	       .	       | |  > CONFIG_SYS_NIOS_CPU_VEC_SIZE
-	       |	       .	       | | |   = 0x00000100
-	       |	       .	       | | /
-  0x008fff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE
-  0x008fff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK
-	       |	       .	       | | \
-	       |	       .	       | | |
-	       |	       .	       | |  > stack area
-	       |	       .	       | | |
-	       |	       .	       | | V
-	       |	       .	       | |
-  SRAM	       |	       .	       |  > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
-	       |	       .	       | |   = 0x00100000
-	       |			       | /
-  0x00800000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SRAM_BASE
-  0x00800000 ---8-------------4|3-------------0-
-	       |  sector 127		       | \
-    + 0x7f0000 |- - - - - - - - - - - - - - - -| |
-	       |	       :	       | |
-  Flash	       |-   -	-   -  :  -   -	  -   -|  > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
-	       |  sector 1     :	       | |   = 0x00800000
-    + 0x010000 |- - - - - - - - - - - - - - - -| |
-	       |  sector 0 (size = 0x10000)    | /
-  0x00000000 ---8-------------4|3-------------0-    CONFIG_SYS_NIOS_CPU_FLASH_BASE
-
-
-===============================================================================
-	F L A S H   M E M O R Y	  A L L O C A T I O N
-===============================================================================
-
-  0x00800000 ---8-------------4|3-------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  SAFE	       |	       :	       |  > 2 MByte
-  FPGA conf.   |	       :	       | |    (NOT usable by software)
-	       |	       :	       | /
-  0x00600000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-  USER	       |	       :	       |  > 2 MByte
-  FPGA conf.   |	       :	       | |    (NOT usable by software)
-	       |	       :	       | /
-  0x00400000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-  WEB pages    |	       :	       |  > 2 MByte
-	       |	       :	       | |    (provisory usable)
-	       |	       :	       | /
-  0x00200000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-	       |	       :	       |  > 2 MByte free for use
-  0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
-	       |	       :	       | /
-  0x00000000 ---8-------------4|3-------------0-
-
-
-===============================================================================
-	R E F E R E N C E S
-===============================================================================
-[1]	http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s40.pdf
-[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
-[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
-[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
-[5]	http://www.opencores.org/projects/ata/
-	http://www.t13.org/index.html
-
-
-===============================================================================
-Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.dk20k200_std32 b/doc/README.dk20k200_std32
deleted file mode 100644
index fc2d2a3874..0000000000
--- a/doc/README.dk20k200_std32
+++ /dev/null
@@ -1,242 +0,0 @@
-
-===============================================================================
-	C P U ,	  M E M O R Y ,	  I N / O U T	C O M P O N E N T S
-===============================================================================
-see also [1]-[4]
-
-CPU:	"standard_32"
-	32 bit NIOS for 33.333 MHz (nasys_clock_freq = 33333000)
-	256 Byte for register file (15 levels)
-	no instruction cache
-	no data cache
-	1 KByte On Chip ROM with GERMS boot monitor
-	no On Chip RAM
-	MSTEP multiplier
-	no Debug Core
-	no On Chip Instrumentation (OCI) enabled
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_CLK	     = 50000000
-			CONFIG_SYS_NIOS_CPU_ICACHE	     = 0
-			CONFIG_SYS_NIOS_CPU_DCACHE	     = 0
-			CONFIG_SYS_NIOS_CPU_REG_NUMS	     = 256
-			CONFIG_SYS_NIOS_CPU_MUL	     = 0
-			CONFIG_SYS_NIOS_CPU_MSTEP	     = 1
-			CONFIG_SYS_NIOS_CPU_DBG_CORE	     = 0
-
-IRQ:	 Nr.  | used by
-	------+--------------------------------------------------------
-	 25   | TIMER0	  |  CONFIG_SYS_NIOS_CPU_TIMER0_IRQ = 25
-	 26   | UART0	  |  CONFIG_SYS_NIOS_CPU_UART0_IRQ  = 26
-	 27   | PIO2	  |  CONFIG_SYS_NIOS_CPU_PIO2_IRQ   = 27
-	 28   | UART1	  |  CONFIG_SYS_NIOS_CPU_UART1_IRQ  = 28    (debug)
-
-MEMORY:	  1 MByte Flash
-	256 KByte SRAM
-	(SDRAM with standard SODIMM only)
-
-Timer:	TIMER0: high priority programmable timer (IRQ25)
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_TICK_TIMER	     = 0
-
-PIO:	 Nr.  | description
-	------+--------------------------------------------------------
-	 PIO0 | SEVENSEG:  16 outputs for user seven segment display
-	 PIO1 | LED:	    8 outputs for user LEDs
-	 PIO2 | BUTTON:	    4 inputs for user push buttons (IRQ27)
-	 PIO3 | LCD:	   11 in/outputs for ASCII LCD
-
-	U-Boot CFG:	CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO    = 0
-			CONFIG_SYS_NIOS_CPU_LED_PIO	     = 1
-			CONFIG_SYS_NIOS_CPU_BUTTON_PIO	     = 2
-			CONFIG_SYS_NIOS_CPU_LCD_PIO	     = 3
-
-UART:	UART0: fixed baudrate of 115200, fixed protocol 8N2,
-	       without handshake RTS/CTS (IRQ26)
-	UART1: fixed baudrate of 115200, fixed protocol 8N1,
-	       without handshake RTS/CTS (IRQ28)
-
-
-===============================================================================
-	M E M O R Y   M A P
-===============================================================================
-
-- - - - - - - - - - -	external memory	  - - - - - - - - - - - - - - - - - - -
-
-  0x00200000 ---15------------8|7-------------0-
-	       |  sector 18		       | \
-    + 0x0f0000 |- - - - - - - - - - - - - - - -| |
-	       |	       :	       | |
-  Flash	       |-   -	-   -  :  -   -	  -   -| |
-	       |  sector 5     :	       | |
-    + 0x020000 |-   -	-   -  -  -   -	  -   -| |
-	       |  sector 4 (size = 0x10000)    | |
-    + 0x010000 |- - - - - - - - - - - - - - - -|  > CONFIG_SYS_NIOS_CPU_FLASH_SIZE
-	       |  sector 3 (size = 0x08000)    | |   = 0x00100000
-    + 0x008000 |- - - - - - - - - - - - - - - -| |
-	       |  sector 2 (size = 0x02000)    | |
-    + 0x006000 |- - - - - - - - - - - - - - - -| |
-	       |  sector 1 (size = 0x02000)    | |
-    + 0x004000 |- - - - - - - - - - - - - - - -| |
-	       |  sector 0 (size = 0x04000)    | /
-  0x00100000 ---15------------8|7-------------0-    CONFIG_SYS_NIOS_CPU_FLASH_BASE
-	       |			       |
-	       :	      gap	       :
-	       |			       |
-  0x00080000 ---32-----------16|15------------0-
-  0x00080000 --+32-----------16|15------------0+
-	       |	       .	       | \ \
-	       |	       .	       | | |
-	       |	       .	       | |  > CONFIG_SYS_NIOS_CPU_VEC_SIZE
-	       |	       .	       | | |   = 0x00000100
-	       |	       .	       | | /
-  0x0007ff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_VEC_BASE
-  0x0007ff00   |- - - - - - - - - - - - - - - -+-|- CONFIG_SYS_NIOS_CPU_STACK
-	       |	       .	       | | \
-	       |	       .	       | | |
-	       |	       .	       | |  > stack area
-	       |	       .	       | | |
-	       |	       .	       | | V
-	       |	       .	       | |
-  SRAM	       |	       .	       |  > CONFIG_SYS_NIOS_CPU_SRAM_SIZE
-	       |	       .	       | |   = 0x00040000
-	       |			       | /
-  0x00040000 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_SRAM_BASE
-	       |			       |
-	       :	      gap	       :
-	       :			       :
-
-- - - - - - - - - - -	  on chip i/o	  - - - - - - - - - - - - - - - - - - -
-
-	       :			       :
-	       :	      gap	       :
-	       |			       |
-  0x00000400 ---32-----------16|15------------0-
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART1	       |		     (unused)  |  > 0x00000020
-  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
-	       |  control (10 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (10 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (8 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (8 bit)	 (ro)  | /
-  0x000004c0 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART1
-	       |			       |
-	       :	      gap	       :
-	       |			       |
-  0x00000490 ---32-----------16|15------------0-
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO3	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (11 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (11 bit)		 (rw)  | /
-  0x00000480 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO3
-	       |  edgecapture (12 bit)	 (rw)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO2	       |  interruptmask (12 bit) (rw)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (12 bit)		 (ro)  | /
-  0x00000470 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO2
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO1	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |  direction (2 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (2 bit)		 (rw)  | /
-  0x00000460 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO1
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |  snaph (16 bit)	 (rw)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  TIMER0       |  snapl (16 bit)	 (rw)  | |
-  [3]	+ 0x10 |- - - - - - - - - - - - - - - -|  > 0x00000020
-	       |  periodh (16 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  periodl (16 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  control (4 bit)	 (rw)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  status (2 bit)	 (rw)  | /
-  0x00000440 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_TIMER0
-	       |		     (unused)  | \
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-  PIO0	       |		     (unused)  | |
-  [4]	+ 0x08 |- - - - - - - - - - - - - - - -|  > 0x00000010
-	       |		     (unused)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  data (16 bit)		 (wo)  | /
-  0x00000420 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_PIO0
-	       |		     (unused)  | \
-	+ 0x1c |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x18 |- - - - - - - - - - - - - - - -| |
-	       |		     (unused)  | |
-	+ 0x14 |- - - - - - - - - - - - - - - -| |
-  UART0	       |		     (unused)  |  > 0x00000020
-  [2]	+ 0x10 |- - - - - - - - - - - - - - - -| |
-	       |  control (10 bit)	 (rw)  | |
-	+ 0x0c |- - - - - - - - - - - - - - - -| |
-	       |  status (10 bit)	 (rw)  | |
-	+ 0x08 |- - - - - - - - - - - - - - - -| |
-	       |  txdata (8 bit)	 (wo)  | |
-	+ 0x04 |- - - - - - - - - - - - - - - -| |
-	       |  rxdata (8 bit)	 (ro)  | /
-  0x00000400 ---32-----------16|15------------0-    CONFIG_SYS_NIOS_CPU_UART0
-
-- - - - - - - - - - -	on chip memory	  - - - - - - - - - - -
-
-  0x00000400 ---32-----------16|15------------0-
-	       |	       :	       | \
-	       |	       :	       | |
-  GERMS	       |	       :	       |  > na_boot_monitor_rom_size
-	       |	       :	       | |   = 0x00000400
-	       |	       :	       | /
-  0x00000000   |- - - - - - - - - - - - - - - -+- - nasys_reset_address
-  0x00000000 ---32-----------16|15------------0-    na_boot_monitor_rom
-
-
-===============================================================================
-	F L A S H   M E M O R Y	  A L L O C A T I O N
-===============================================================================
-
-  0x00200000 ---15------------8|7-------------0-
-	       |	       :	       | \
-  SAFE	       |	       :	       |  > 256 KByte
-  FPGA conf.   |	       :	       | /    (NOT usable by software)
-  0x001c0000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-  USER	       |	       :	       |  > 256 KByte
-  FPGA conf.   |	       :	       | /    (NOT usable by software)
-  0x00180000 --+- - - - - - - -:- - - - - - - -+-
-	       |	       :	       | \
-	       |	       :	       | |
-	       |	       :	       |  > 512 KByte free for use
-  0x00140000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
-	       |	       :	       | /
-  0x00100000 ---15------------8|7-------------0-
-
-
-===============================================================================
-	R E F E R E N C E S
-===============================================================================
-[1]	http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf
-[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
-[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
-[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
-
-
-===============================================================================
-Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.nios b/doc/README.nios
deleted file mode 100644
index 5628144600..0000000000
--- a/doc/README.nios
+++ /dev/null
@@ -1,366 +0,0 @@
-
-			   U-Boot for Nios-32
-
-		    Last Update: February 1, 2004
-====================================================================
-
-This file contains information regarding U-Boot and the Altera
-Nios CPU. For information regarding U-Boot and the Nios Development
-Kits see:
-
-  * Cyclone Edition (DK-1C20), see doc/README.dk1c20
-  * Stratix Edition (DK-1S10), see doc/README.dk1s10 (TODO)
-  * Stratix Edition (DK-1S40), see doc/README.dk1s40 (TODO)
-  * Stratix Edition (DK-20K200), see doc/README.dk20k200 (TODO)
-
-For informations regarding Nios Development Kit hardware overview
-and the NIOS CPU standard configuration of all known boards made by
-Altera see:
-
-  * Development Kit (DK) hardware overview, see doc/README.nios_DK
-  * NIOS CPU standard_32 at DK-1C20, see doc/README.dk1c20_std32
-  * NIOS CPU standard_32 at DK-1S10, see doc/README.dk1s10_std32
-  * NIOS CPU standard_32 at DK-1S40, see doc/README.dk1s40_std32
-  * NIOS CPU standard_32 at DK-20K200, see doc/README.dk20k200_std32
-
-For those interested in contributing ... see HELP WANTED below.
-
-
-1. OVERVIEW
-------------
-
-U-Boot has been successfully tested on the Nios Cyclone development
-board using both the 'safe' and 'standard 32' configurations with
-Nios CPU revision 3.1 (CPU_ID = 0x3018). U-Boot can be used with
-or without the GERMS monitor. The initial version of U-Boot for the
-Cyclone development kit is about 60 Kbyte and will fit in a single
-sector of on-board FLASH. Only the Nios 32-bit CPU is supported.
-
-1.1 GERMS Monitor
-------------------
-If GERMS is just not enough, then U-Boot is a great antibiotic.
-You will be very pleased with its high degree of configurability
-and its rich feature set.
-
-A few of the most obvious limitations of GERMS are overcome by
-using U-Boot (See 'Brain Damage'). Most notably, you can use
-minicom or Hyperterminal (duh).
-
-1.2 Altera Source Code
------------------------
-The Nios port does NOT include ANY sources that Altera has the
-copyright. This was a conscious decision ... not an accident.
-The Altera license is not clear in terms of distributing Altera
-sources (when altera silicon is not involved). This isn't really
-a problem as little, if any, of the Altera source contains
-features that are not already available in U-Boot.
-
-1.3 Debugging via OCI
----------------------
-The Nios port supports debugging with gdb and/or nios-console
-via the JTAG port. Stubs for debugging with gdb via the serial
-port are not currently implemented.
-
-
-2. CONFIGURATION OPTIONS/SETTINGS
-----------------------------------
-
-2.1 Nios-specific Options/Settings
------------------------------------
-All configuration options/settings that are specific to Nios begin
-with "CONFIG_NIOS_", "CONFIG_SYS_NIOS_", or "CONFIG_SYS_NIOS_CPU_".
-
-The configuration follows a two-stage process. In the first stage
-the NIOS CPU core will defined like defined in Alteras SOPC Builder.
-At this point we use the "CONFIG_SYS_NIOS_CPU_" defines exclusively. For
-more informations about all the definitions you have to setup see
-into current board configurations and doc/README.nios_CFG_NIOS_CPU.
-
-In second stage we bring the NIOS CPU configuration in relation to
-U-Boot configuration options/settings. The following is a list of
-currently defined Nios-specific options/parameters used inside of
-U-Boot. If any options are related to Standard-32 Nios SDK
-excalibur.h definitions, the related definition follows the
-description).
-
-CONFIG_NIOS -- defined for all Nios-32 boards.
-
-CONFIG_SYS_NIOS_CONSOLE -- the base address of the console UART or the JTAG
-	stdio port. To enable a console via JTAG, define
-	CONFIG_CONSOLE_JTAG and set CGF_NIOS_CONSOLE to the base address
-	of the JTAG stdio port (normally OCI base + 0x00fa). Then
-	run nios-console with the -w option.
-	(standard-32: nasys_uart_0 resp. na_uart1_base).
-
-CONFIG_SYS_NIOS_FIXEDBAUD -- defined if the console UART PTF fixed_baud
-	parameter is set to '1'.
-
-CONFIG_SYS_NIOS_MULT_HW -- use full hardware multiply (not yet implemented).
-
-CONFIG_SYS_NIOS_MULT_MSTEP -- use hardware assisted multiply using the
-	MSTEP instruction (not yet implemented).
-
-CONFIG_SYS_NIOS_TMRBASE -- the base address of the timer used to support
-	xxx_timer routines (e.g. set_timer(), get_timer(), etc.).
-	(standard-32: nasys_timer_1 resp. na_lo_priority_timer2_base).
-
-CONFIG_SYS_NIOS_TMRIRQ -- the interrupt request (vector number) assigned to
-	the timer. (standard-32: nasys_timer_1_irq resp.
-	na_low_priority_timer2_irq).
-
-CONFIG_SYS_NIOS_TMRMS -- the period of the timer in milliseconds.
-
-CONFIG_SYS_NIOS_TMRCNT -- the preloadable counter value for the timer if it has
-	no fixed period.
-
-CONFIG_SYS_NIOS_ASMIBASE -- the base address of the ASMI peripheral.
-	(standard-32: na_asmi_base).
-
-CONFIG_SYS_NIOS_SPIBASE -- the base address of the SPI master (!) peripheral.
-	(nasys_spi_0)
-
-CONFIG_SYS_NIOS_SPIBITS -- the amount of configured SPI data bits in PTF.
-	This value can be 8 or 16 only! (PTF: databits)
-
-
-2.2 Differences in U-Boot Options/Settings
--------------------------------------------
-Some 'standard' U-Boot options/settings are treated differently in
-the Nios port. These are described below.
-
-CONFIG_SYS_GBL_DATA_OFFSET -- in the Nios port, this is the offset of the
-	global data structure in the Nios memory space. More simply,
-	the address of global data.
-
-
-3. ASSEMBLY CODING
--------------------
-
-In browsing the assembly source files, you may notice the absence
-of the 'magic macros' (e.g. MOVIA, MOVIP, ADDIP etc.). This is
-deliberate. The documentation for the magic macros is scant and
-it is hard to find ... it does not appear in the Nios programmer's
-manual, nor does it appear in the assembler manual. Regardless,
-the macros actually do very little to improve readability anyway.
-
-With this in mind, all assembler modules use only instructions that
-appear in the Nios programmer's manual OR are directly supported
-by the nios-elf toolchain. For example, the 'dec %rB' instruction
-is an alias for 'subi %rB,1' that is supported by the assembler
-but does not appear in the programmer's manual.
-
-
-4. BOOT PROCESS
----------------
-
-4.1 Boot process over GERMS
----------------------------
-When the NIOS CPU catch a reset signal it will begin to be running
-code from CONFIG_SYS_NIOS_CPU_RST_VECT. Normally at this place it will
-find the GERMS monitor. That's the case for the generic NIOS CPU
-configuration "standard_32". When the GERMS monitor starts running,
-it performs important system initializations and then looks for
-executable code in flash, using the following steps:
-
-    1. Examining the two bytes at CONFIG_SYS_NIOS_CPU_FLASH_BASE + 0x04000C.
-    2. Examining the button 0 on the PIO CONFIG_SYS_NIOS_CPU_BUTTON_PIO.
-    3. If the button is not pressed and the two bytes contain 'N'
-       and 'i', the monitor executes a CALL to location
-       CONFIG_SYS_NIOS_CPU_FLASH_BASE + 0x040000.
-    4. If the code is not executed in step 3 or the code returns,
-       then prints an 8-digit version number to STDOUT and waits for
-       user commands from STDIN.
-
-In normal case, for "standard_32", STDIN and STDOUT are the first
-serial port.
-
-4.2 Return to GERMS command line
---------------------------------
-During the boot process, the GERMS monitor checks for the existence
-of application software in flash memory. If found, the processor
-immediately executes the code. To return program execution to the
-GERMS monitor (that is, avoid running code stored in flash memory):
-
-    1. Hold down CONFIG_SYS_NIOS_CPU_BUTTON_PIO, button number 0.
-    2. Press then release the CPU reset button.
-    3. Release CONFIG_SYS_NIOS_CPU_BUTTON_PIO, button number 0.
-
-
-5. DEBUGGING WITH GDB
----------------------
-
-Debug sessions using gdb are currently supported only via JTAG. The
-stubs for debugging via a serial port are not implemented. To enable
-the gdb JTAG stubs, simply reference _brkpt_hw_int and _brkpt_sw_int
-at vector table offsets 3 and 4, respectively. For an example, see
-board/altera/dk1c20/vectors.S.
-
-5.1 Vector Table Initialization and ROM Stubs
----------------------------------------------
-If CONFIG_ROM_STUBS is defined, the debug breakpoint and single step
-entries in the vector table are restored to their initial values
-immediately _after_ initializing the vector table. Defining this macro
-is useful when ROM-based stubs are implemented.
-
-NOTE: The default GERMS monitor does NOT implement gdb stubs, nor does
-it initialize the vector table. Therefore, when debugging U-Boot, you
-should NOT set a software breakpoint prior to vector table initialization.
-
-5.2 Starting a Debug Session
-----------------------------
-If you're not familiar with gdb, you follow these step-by-step instructions.
-These instructions are NOT the only way to start a debug session, but they
-cover most of the individual functions to get you started.
-
-	1.  Start the JTAG gdb server. Open a Nios shell window and start
-	the server. When the server is started you must provide the base
-	address of the OCI core. For example, when using the Cyclone
-	development kit (DK1C20):
-
-		$ nios-gdb-server --ocibase=0x00920800 --tcpport=2342
-
-	2.  Start gdb. Open a Nios shell window, change to the top-level
-	U-Boot directory and start gdb, specifying the u-boot elf file:
-
-		$ nios-elf-gdb u-boot
-
-	3.  Update target settings. From the file menu, select
-	"Target Settings ..." and select the following, then click 'Ok':
-
-		Target:	Remote/TCP
-		Port :	2342   (same as in step 1)
-		Display download dialog: checked
-		All other check boxes: unchecked
-
-	4.  Connect to the target. Select menu: 'Run->Connect to target'.
-	You should see a dialog box indicating the you successfully connected
-	to the target.
-
-	5.  Download U-Boot. Select menu: 'Run->Download'.
-
-	6.  Open a gdb console window and set the source directory paths.
-	Select menu: 'View->Console'. In the console window, enter the
-	following commands, then close the console window:
-
-		(gdb) directory common
-		(gdb) directory arch/nios/cpu
-		(gdb) directory arch/nios/lib
-		(gdb) directory board/altera/dk1c20
-
-	Note that the last command is for the DK1C20 board only. If you
-	are using another board, specify that board's directory.
-
-	7.  Open the file board.c (using the file menu in the lower
-	left hand corner). Scroll to the board_init() routine and set
-	a breakpoint.
-
-	8. Run U-Boot. Just click on the run icon, or select menu:
-	'Run->Run'. U-Boot should start running, then break at your
-	breakpoint.
-
-	9.  Have fun & start learning more about gdb.
-
-
-5.3 For advanced Users
-----------------------
-A few notes for those more familiar with gdb.
-
-	-Serial port stubs are not implemented. Sorry, but it's just not
-	worth _my_ effort. The JTAG stubs work great and are ridiculously
-	simple to implement.
-
-	-If you need to debug the early startup code (prior to the vector
-	table initialization), use the nios-console debugger.
-
-	- Connect, download & run -- there are some problems here. Connect
-	download and run seperately to avoid trouble.
-
-6. BRAIN DAMAGE
-----------------
-
-This section describes some of the unfortunate and avoidable aspects
-of working with the Nios CPU ... and some things you can do to
-reduce your pain.
-
-6.1 GERMS doesn't work with Hyperterminal
-------------------------------------------
-GERMS doesn't do CR/LF mapping that is compatible with Hyperterminal
-(or minicom) -- geez. Regardless of you opion of Hyperterminal, this
-sad design decision is remedied by using U-Boot.
-
-6.2 cygwin Incompatibility
----------------------------
-The version of cygwin distributed with the nios GNUPro toolchain is
-out-of-date and incompatible with the latest cygwin distributions.
-In addition, many of the standard utilities are very dated as well.
-If you try to download and build the lastest version of grep for
-example, you'll quickly realize that a native gcc is not available
-(the next topic) which leads to U-Boot build problems (following
-topic).
-
-The solution ... well, you can wait for Altera ... or build as
-set of tools for linux.
-
-6.3 No native gcc
-------------------
-I'm not sure how this one slipped through the cracks ... but it is
-a real pain. Basically, if you want to build anything for the native
-environment -- forget it! A native (cygwin) gcc is not distributed,
-and the old version of cygwin makes locating one challenging.
-
-The solution ... same as above. Just download the gcc source from
-Altera and build up a set of cross tools for your favorite linux
-distro. Anybody who wants to use an already precompiled NIOS cross
-toolchain can it found in the CDK4NIOS project hosted by Source
-Forge at http://cdk4nios.sourceforge.net.
-
-6.4 Can't build default U-Boot
--------------------------------
-By default, when you build U-Boot you will be building some native
-tools along with the target elf, bin, and srec files. Without a
-native gcc, this (obviously) causes problems.
-
-For developers using the Altera cygwin tools you can remove the
-'tools' directory from SUBDIRS in the top-level Makefile. You will
-also have to edit common/Makefile:
-
-Replace:
-env_embedded.o: env_embedded.c ../tools/envcrc
-	$(CC) $(AFLAGS) -Wa,--no-warn \
-		-DENV_CRC=$(shell ../tools/envcrc) \
-		-c -o $@ env_embedded.c
-
-With:
-env_embedded.o: env_embedded.c
-	$(CC) $(AFLAGS) -Wa,--no-warn \
-		-DENV_CRC=0 \
-		-c -o $@ env_embedded.c
-
-BTW, thats a 'zero' ... not the letter 'O'. And not that the
-"../tools/envcrc" dependency is removed.
-
-
-7. HELP WANTED
----------------
-
-There are plenty of areas where help is needed. Here's are some ideas
-for those interested in contributing:
-
--CompactFlash. Port & test CF/FAT.
-
--Bedbug. Develop bedbug for Nios ... or at least provide a disassemble
- command.
-
--Add boot support for ucLinux (niosnommu).
-
--Implement (don't copy Altera code) the __mulxx routines using the
- MSTEP and MUL instructions (e.g. CONFIG_SYS_NIOS_MULT_HW and CONFIG_SYS_NIOS_MULT_MSTEP).
-
-
-Regards,
-
---Scott
-<smcnutt@psyent.com>
-
---Stephan
-<linz@li-pro.net>
diff --git a/doc/README.nios_CONFIG_SYS_NIOS_CPU b/doc/README.nios_CONFIG_SYS_NIOS_CPU
deleted file mode 100644
index 3547c343bd..0000000000
--- a/doc/README.nios_CONFIG_SYS_NIOS_CPU
+++ /dev/null
@@ -1,140 +0,0 @@
-
-===============================================================================
-	C F G _ N I O S _ C P U _ *   v s .   N I O S	S D K
-===============================================================================
-
-When ever you have to make a new NIOS CPU configuration you can use this table
-as a reference list to the original NIOS SDK symbols made by Alteras SOPC
-Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc.
-Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description
-(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO.
-
-C O R E					N I O S	  S D K			[1],[7]
--------------------------------------------------------------------------------
-CONFIG_SYS_NIOS_CPU_CLK					nasys_clock_freq
-CONFIG_SYS_NIOS_CPU_ICACHE					nasys_icache_size
-CONFIG_SYS_NIOS_CPU_DCACHE					nasys_dcache_size
-CONFIG_SYS_NIOS_CPU_REG_NUMS					nasys_nios_num_regs
-CONFIG_SYS_NIOS_CPU_MUL					__nios_use_multiply__
-CONFIG_SYS_NIOS_CPU_MSTEP					__nios_use_mstep__
-CONFIG_SYS_NIOS_CPU_STACK					nasys_stack_top
-CONFIG_SYS_NIOS_CPU_VEC_BASE					nasys_vector_table
-CONFIG_SYS_NIOS_CPU_VEC_SIZE					nasys_vector_table_size
-CONFIG_SYS_NIOS_CPU_VEC_NUMS
-CONFIG_SYS_NIOS_CPU_RST_VECT					nasys_reset_address
-CONFIG_SYS_NIOS_CPU_DBG_CORE					nasys_debug_core
-CONFIG_SYS_NIOS_CPU_RAM_BASE		na_onchip_ram_64_kbytes
-CONFIG_SYS_NIOS_CPU_RAM_SIZE		na_onchip_ram_64_kbytes_size
-CONFIG_SYS_NIOS_CPU_ROM_BASE		na_boot_monitor_rom
-CONFIG_SYS_NIOS_CPU_ROM_SIZE		na_boot_monitor_rom_size
-CONFIG_SYS_NIOS_CPU_OCI_BASE					nasys_oci_core
-CONFIG_SYS_NIOS_CPU_OCI_SIZE
-CONFIG_SYS_NIOS_CPU_SRAM_BASE		na_ext_ram		nasys_program_mem
-							nasys_data_mem
-CONFIG_SYS_NIOS_CPU_SRAM_SIZE		na_ext_ram_size		nasys_program_mem_size
-							nasys_data_mem_size
-CONFIG_SYS_NIOS_CPU_SDRAM_BASE		 na_sdram
-CONFIG_SYS_NIOS_CPU_SDRAM_SIZE		 na_sdram_size
-CONFIG_SYS_NIOS_CPU_FLASH_BASE		 na_ext_flash		nasys_main_flash
-							nasys_am29lv065d_flash_0
-							nasys_flash_0
-CONFIG_SYS_NIOS_CPU_FLASH_SIZE	    na_ext_flash_size		nasys_main_flash_size
-
-T I M E R				N I O S	  S D K			    [3]
--------------------------------------------------------------------------------
-CONFIG_SYS_NIOS_CPU_TIMER_NUMS					nasys_timer_count
-CONFIG_SYS_NIOS_CPU_TIMER[0-9]					nasys_timer_[0-9]
-CONFIG_SYS_NIOS_CPU_TIMER[0-9]_IRQ				nasys_timer_[0-9]_irq
-CONFIG_SYS_NIOS_CPU_TIMER[0-9]_PER				[ptf]:period
-							[ptf]:period_units
-							[ptf]:mult
-CONFIG_SYS_NIOS_CPU_TIMER[0-9]_AR				[ptf]:always_run
-CONFIG_SYS_NIOS_CPU_TIMER[0-9]_FP				[ptf]:fixed_period
-CONFIG_SYS_NIOS_CPU_TIMER[0-9]_SS				[ptf]:snapshot
-
-U A R T					N I O S	  S D K			    [2]
--------------------------------------------------------------------------------
-CONFIG_SYS_NIOS_CPU_UART_NUMS					nasys_uart_count
-CONFIG_SYS_NIOS_CPU_UART[0-9]					nasys_uart_[0-9]
-CONFIG_SYS_NIOS_CPU_UART[0-9]_IRQ				nasys_uart_[0-9]_irq
-CONFIG_SYS_NIOS_CPU_UART[0-9]_BR				[ptf]:baud
-CONFIG_SYS_NIOS_CPU_UART[0-9]_DB				[ptf]:data_bits
-CONFIG_SYS_NIOS_CPU_UART[0-9]_SB				[ptf]:stop_bits
-CONFIG_SYS_NIOS_CPU_UART[0-9]_PA				[ptf]:parity
-CONFIG_SYS_NIOS_CPU_UART[0-9]_HS				[ptf]:use_cts_rts
-CONFIG_SYS_NIOS_CPU_UART[0-9]_EOP				[ptf]:use_eop_register
-
-P I O					N I O S	  S D K			    [4]
--------------------------------------------------------------------------------
-CONFIG_SYS_NIOS_CPU_PIO_NUMS					nasys_pio_count
-CONFIG_SYS_NIOS_CPU_PIO[0-9]					nasys_pio_[0-9]
-CONFIG_SYS_NIOS_CPU_PIO[0-9]_IRQ				nasys_pio_[0-9]_irq
-CONFIG_SYS_NIOS_CPU_PIO[0-9]_BITS				[ptf]:Data_Width
-CONFIG_SYS_NIOS_CPU_PIO[0-9]_TYPE				[ptf]:has_tri
-							[ptf]:has_out
-							[ptf]:has_in
-CONFIG_SYS_NIOS_CPU_PIO[0-9]_CAP				[ptf]:capture
-CONFIG_SYS_NIOS_CPU_PIO[0-9]_EDGE				[ptf]:edge_type
-CONFIG_SYS_NIOS_CPU_PIO[0-9]_ITYPE				[ptf]:irq_type
-
-S P I					N I O S	  S D K			    [6]
--------------------------------------------------------------------------------
-CONFIG_SYS_NIOS_CPU_SPI_NUMS					nasys_spi_count
-CONFIG_SYS_NIOS_CPU_SPI[0-9]					nasys_spi_[0-9]
-CONFIG_SYS_NIOS_CPU_SPI[0-9]_IRQ				nasys_spi_[0-9]_irq
-CONFIG_SYS_NIOS_CPU_SPI[0-9]_BITS				[ptf]:databits
-CONFIG_SYS_NIOS_CPU_SPI[0-9]_MA				[ptf]:ismaster
-CONFIG_SYS_NIOS_CPU_SPI[0-9]_SLN				[ptf]:numslaves
-CONFIG_SYS_NIOS_CPU_SPI[0-9]_TCLK				[ptf]:targetclock
-CONFIG_SYS_NIOS_CPU_SPI[0-9]_TDELAY				[ptf]:targetdelay
-CONFIG_SYS_NIOS_CPU_SPI[0-9]_*					[ptf]:*
-
-I D E					N I O S	  S D K
--------------------------------------------------------------------------------
-CONFIG_SYS_NIOS_CPU_IDE_NUMS					nasys_usersocket_count
-CONFIG_SYS_NIOS_CPU_IDE[0-9]					nasys_usersocket_[0-9]
-
-A S M I					N I O S	  S D K			    [5]
--------------------------------------------------------------------------------
-CONFIG_SYS_NIOS_CPU_ASMI_NUMS					nasys_asmi_count
-CONFIG_SYS_NIOS_CPU_ASMI[0-9]					nasys_asmi_[0-9]
-CONFIG_SYS_NIOS_CPU_ASMI[0-9]_IRQ				nasys_asmi_[0-9]_irq
-
-E t h e r n e t	  ( L A N )		N I O S	  S D K
--------------------------------------------------------------------------------
-CONFIG_SYS_NIOS_CPU_LAN_NUMS
-CONFIG_SYS_NIOS_CPU_LAN[0-9]_BASE	na_lan91c111
-CONFIG_SYS_NIOS_CPU_LAN[0-9]_OFFS				LAN91C111_REGISTERS_OFFSET
-CONFIG_SYS_NIOS_CPU_LAN[0-9]_IRQ	na_lan91c111_irq
-CONFIG_SYS_NIOS_CPU_LAN[0-9]_BUSW				LAN91C111_DATA_BUS_WIDTH
-CONFIG_SYS_NIOS_CPU_LAN[0-9]_TYPE
-
-s y s t e m   c o m p o s i n g		N I O S	  S D K
--------------------------------------------------------------------------------
-CONFIG_SYS_NIOS_CPU_TICK_TIMER		(na_low_priority_timer2)
-CONFIG_SYS_NIOS_CPU_USER_TIMER		(na_timer1)
-CONFIG_SYS_NIOS_CPU_BUTTON_PIO		(na_button_pio)
-CONFIG_SYS_NIOS_CPU_LCD_PIO		(na_lcd_pio)
-CONFIG_SYS_NIOS_CPU_LED_PIO		(na_led_pio)
-CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO	(na_seven_seg_pio)
-CONFIG_SYS_NIOS_CPU_RECONF_PIO		(na_reconfig_request_pio)
-CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO	(na_cf_present_pio)
-CONFIG_SYS_NIOS_CPU_CFPOWER_PIO	(na_cf_power_pio)
-CONFIG_SYS_NIOS_CPU_CFATASEL_PIO	(na_cf_ata_select_pio)
-CONFIG_SYS_NIOS_CPU_USER_SPI		(na_spi)
-
-
-===============================================================================
-	R E F E R E N C E S
-===============================================================================
-[1]	http://www.altera.com/literature/ds/ds_nioscpu.pdf
-[2]	http://www.altera.com/literature/ds/ds_nios_uart.pdf
-[3]	http://www.altera.com/literature/ds/ds_nios_timer.pdf
-[4]	http://www.altera.com/literature/ds/ds_nios_pio.pdf
-[5]	http://www.altera.com/literature/ds/ds_nios_asmi.pdf
-[6]	http://www.altera.com/literature/ds/ds_nios_spi.pdf
-[7]	http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf
-
-
-===============================================================================
-Stephan Linz <linz@li-pro.net>
diff --git a/doc/README.nios_DK b/doc/README.nios_DK
deleted file mode 100644
index b119d76682..0000000000
--- a/doc/README.nios_DK
+++ /dev/null
@@ -1,192 +0,0 @@
-
-===============================================================================
-	H A R D W A R E	  O V E R V I E W
-===============================================================================
-===============|===============|===============|===============|===============
-	       |  DK20K200     |  DK1C20       |  DK1S10       |  DK1S40
----------------|---------------|---------------|---------------|---------------
-	       |	       |	       |	       |
-  Schem. Nr.   | Nios Dev.Brd. |  P06-08713-00 |  P06-08468-01 |  P06-09178-00
-	 Rev.  | pilot.	       |  01	       |  01	       |  00
-	 Date  | 2001/02/06    |  2003/02/20   |  2003/02/14   |  2003/05/14
-[1]	       |	       |	       |	       |
-===============|===============|===============|===============|===============
-	       |	       |	       |	       |
-  FPGA	       | "APEX"	       | "Cyclon"      | "Stratix"     | "Stratix"
-	       |  EP20K200E    |  EP1C20       |  EP1S10       |  EP1S40
-	       |	       |	       |
-	       | (484 FBGA)    | (400 FBGA)    | (780 FBGA)
-[2],[3],[4]    |	       |	       |
----------------|---------------|---------------|---------------|---------------
-	       |	       |
-  Clock (OSC)  |  33.333 MHz   |  50 MHz
-	       |	       | (with ext. supply)
-	       |
-	       |  PI49FCT3805
-[5]	       |
----------------|---------------|---------------|---------------|---------------
-	       |	       |
-  Flash	       |  1 MByte      |  8 MByte
-	       |	       |
-	       |  AM29LV800BB  |  AM29LV065DU120REI
-	       |  8/16 bit bus |  8 bit bus
-	       |  1 chip       |  1 chip
-[6],[7]	       |	       |
----------------|---------------|---------------|---------------|---------------
-	       |	       |	       |
-  serial       |  no such      |  4 MBits      |  no such
-  Flash	       |	       |	       |
-	       |	       |  EPCS4SI8     |
-[8]	       |	       |	       |
----------------|---------------|---------------|---------------|---------------
-	       |	       |
-  Compact      |  no such, as  |  see below: prototype adapter
-  Flash (CF)   |  module only  |
-	       |	       |
----------------|---------------|---------------|---------------|---------------
-	       |	       |
-  SRAM	       |  256 KByte    |  1 MByte
-	       |	       |
-	       |  IDT71V016S   |  IDT71V416S10PH
-	       |  32 bit bus   |  32 bit bus
-	       |  2 chips      |  2 chips
-	       |    interlaced |    interlaced
-[9],[10]       |	       |
----------------|---------------|---------------|---------------|---------------
-	       |	       |
-  SDRAM	       |  SODIMM only  |  16 MByte
-	       |	       |
-	       |	       |  MT48LC4M32B2TG-7
-	       |  64 bit bus   |  32 bit bus
-	       |	       |  1 chip
-[11]	       |	       |
-===============|===============|===============|===============|===============
-	       |	       |
-  serial I/O   |  1 RS232      |  2 RS232
-	       |	       |
-	       |  LTC1386      |  MAX3237CAI
-	       |	       |
-	       |  port 1:      |  port 1:
-	       |   RxD / TxD,  |   RxD / TxD,
-	       |   RTS / CTS   |   RTS / CTS, DTR / DSR, DCD, RI
-	       |	       |
-	       |  ! ! ! ! ! !  |  port 2:      |  port 2:
-	       |  RTS/CTS can  |   RxD / TxD   |   RxD / TxD
-	       |  be RxD/TxD   |	       |   RTS / CTS, DTR / DSR
-	       |  of 2nd port  |	       |   DCD, RI
-[12],[13]      |  ! ! ! ! ! !  |	       |
----------------|---------------|---------------|---------------|---------------
-	       |	       |
-  Ethernet     |  no such, as  |  1 10BaseT / 100BaseT
-	       |  module only  |
-	       |	       |  LAN91C111-NE
-	       |	       |  32 bit bus
-	       |	       |  no external EEPROM
-	       |	       |  LEDA# for link
-	       |	       |  LEDB# for Rx / Tx
-[14]	       |	       |
-===============|===============|===============|===============|===============
-	       |	       |
-  user	       |  8	       |  no such
-  switches     |  SW[7..0]     |
-	       |	       |
----------------|---------------|---------------|---------------|---------------
-	       |
-  user push    |  4
-  buttons      |  PB[3..0]
-	       |
----------------|---------------|---------------|---------------|---------------
-	       |	       |
-  user LEDs    |  2	       |  8
-	       |  LED[1..0]    |  LED[7..0]
-	       |	       |
----------------|---------------|---------------|---------------|---------------
-	       |
-  user seven   |  2
-  segment      |  HEX[1..0][G..A,DP]
-	       |
-===============|===============|===============|===============|===============
-	       |	       |
-  3.3V proto-  |  w/o level    |  no such -- only 5V
-  type adapter |  shift buffer |
-	       |	       |
-	       |  40 I/O pins  |
-	       |  1 card sel.  |
-	       |  1 reset out. |
-	       |  1 OSC clock  |
-	       |  1 CPU clock  |
-	       |  1 clock out. |
-	       |	       |
----------------|---------------|---------------|---------------|---------------
-	       |	       |
-  5V prototype |  with level   |  2 ports -- both card ports supplied with its
-  adapter      |  shift buffer |	     own level shift buffer
-	       |	       |
-	       |  40 I/O pins  |  port 1 & 2:
-	       |  1 card sel.  |   41 I/O pins
-	       |  1 Vee	 ? ? ? |   1 card select
-	       |  1 reset out. |   1 reset output (from dev/board)
-	       |  1 OSC clock  |   1 OSC clock	  (from dev/board)
-	       |  1 CPU clock  |   1 CPU clock	  (from dev/board)
-	       |  1 clock inp. |   1 clock input  (to dev/board)
-	       |	       |
-	       |	       |  (special) port 1:
-	       |	       |   1 CF select
-	       |	       |   1 CF present
-	       |	       |   1 CF ATA select
-	       |	       |   1 CF power
-	       |	       |
-	       |	       |  NOTE: Both card ports are prepared for raw
-	       |	       |	IDE working. You can connect such
-	       |	       |	devices directly to the 40 pin header.
-	       |	       |	The signal PDIAG (passed diagnostic)
-	       |	       |	is not connected to any I/O signal.
-	       |	       |	Card port 1 is hard wired to the on
-	       |	       |	board Copact Flash adapter together
-	       |	       |	with all other signals needed by CF
-	       |	       |	cards. Hot plug should be working too.
-[15],[16]      |	       |
-===============|===============|===============|===============|===============
-	       |	       |
-  config. CPLD |  EPM7064      |  EPM7128
-	       |	       |
-  (alternative |  decition by  |  decision by
-   FPGA conf.) |  jumper       |  push button
-	       |	       |
-	       |  FPGA config. |  FPGA config. |  FPGA config.
-	       |  from Flash   |  from Flash   |  from Flash
-	       |  only	       |  and EPCS4    |  only
-	       |	       |	       |
-===============|===============|===============|===============|===============
-===============================================================================
-
-
-===============================================================================
-	R E F E R E N C E S
-===============================================================================
-[1]	http://www.altera.com/literature/lit-nio.jsp
-[2]	http://www.altera.com/literature/lit-apx.jsp
-[3]	http://www.altera.com/literature/lit-cyc.jsp
-[4]	http://www.altera.com/literature/lit-stx.jsp
-[5]	http://www.pericom.com/pdf/datasheets/PI49FCT3805.pdf
-	http://www.pericom.com/products/clock/psempart.php?productID=PI49FCT3805
-[6]	http://www.amd.com/us-en/FlashMemory/ProductInformation/0,,37_1447_1623_1468^1532,00.html
-	http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21490.pdf
-[7]	http://www.amd.com/us-en/FlashMemory/ProductInformation/0,,37_1447_1623_1468^1596,00.html
-	http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/23544b.pdf
-[8]	http://www.altera.com/literature/lit-config.html
-	http://preview.altera.com/literature/ds/micron.pdf
-[9]	http://www.idt.com/products/pages/Asynchronous_SRAMs-71V016SA.html
-[10]	http://www.idt.com/products/pages/Asynchronous_SRAMs-71V416SL.html
-[11]	http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC4M32B2TG-7
-[12]	http://www.linear.com/prod/datasheet.html?datasheet=33
-	http://www.linear.com/pdf/1386fa.pdf
-[13]	http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1068/ln/en
-	http://pdfserv.maxim-ic.com/en/ds/MAX3222-MAX3241.pdf
-[14]	http://www.smsc.com/main/catalog/lan91c111.html
-[15]	http://www.t13.org/index.html
-[16]	http://www.compactflash.org/faqs/faq.htm
-
-
-===============================================================================
-Stephan Linz <linz@li-pro.net>
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 157936ed53..6d2070758d 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -173,8 +173,7 @@ the '/images' node should have the following layout:
   - arch : Architecture name, mandatory for types: "standalone", "kernel",
     "firmware", "ramdisk" and "fdt". Valid architecture names are: "alpha",
     "arm", "i386", "ia64", "mips", "mips64", "ppc", "s390", "sh", "sparc",
-    "sparc64", "m68k", "nios", "microblaze", "nios2", "blackfin", "avr32",
-    "st200".
+    "sparc64", "m68k", "microblaze", "nios2", "blackfin", "avr32", "st200".
   - entry : entry point address, address size is determined by
     '#address-cells' property of the root node. Mandatory for for types:
     "standalone" and "kernel".