summaryrefslogtreecommitdiffstats
path: root/cpu
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2009-09-17 01:52:37 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-09-24 12:05:29 -0500
commit3c2a67eec8a0facc865b400caca52e7f6b7adf01 (patch)
tree131a11003534635f5ae7a948ee4202e1e2d1c711 /cpu
parent7e4259bba4c56536760e42d32dacfb3233f216fd (diff)
downloadtalos-obmc-uboot-3c2a67eec8a0facc865b400caca52e7f6b7adf01.tar.gz
talos-obmc-uboot-3c2a67eec8a0facc865b400caca52e7f6b7adf01.zip
ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu')
-rw-r--r--cpu/mpc85xx/cpu.c4
-rw-r--r--cpu/mpc85xx/cpu_init.c17
-rw-r--r--cpu/mpc85xx/fdt.c2
3 files changed, 22 insertions, 1 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index bdd9ee4c83..25c04169fd 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -184,7 +184,11 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
*/
unsigned long get_tbclk (void)
{
+#ifdef CONFIG_FSL_CORENET
+ return (gd->bus_clk + 8) / 16;
+#else
return (gd->bus_clk + 4UL)/8UL;
+#endif
}
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a8d83b1c8a..53369349d1 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -136,6 +136,20 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
* initialize a bunch of registers
*/
+#ifdef CONFIG_FSL_CORENET
+static void corenet_tb_init(void)
+{
+ volatile ccsr_rcpm_t *rcpm =
+ (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ volatile ccsr_pic_t *pic =
+ (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
+ u32 whoami = in_be32(&pic->whoami);
+
+ /* Enable the timebase register for this core */
+ out_be32(&rcpm->ctbenrl, (1 << whoami));
+}
+#endif
+
void cpu_init_f (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
@@ -229,6 +243,9 @@ void cpu_init_f (void)
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
+#ifdef CONFIG_FSL_CORENET
+ corenet_tb_init();
+#endif
}
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 61e0fb0636..efb6518822 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -294,7 +294,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_add_enet_stashing(blob);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
- "timebase-frequency", bd->bi_busfreq / 8, 1);
+ "timebase-frequency", get_tbclk(), 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1);
get_sys_info(&sysinfo);
OpenPOWER on IntegriCloud