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| author | Stefan Roese <sr@denx.de> | 2009-09-28 17:33:45 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-02 13:53:37 +0200 |
| commit | fb95169e39f2d03270bed552d27bbb02627a443e (patch) | |
| tree | c94e691e322097c7cdc43943cd3bb05b3e7c760e /cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | |
| parent | d24bd2517a2b847f773453eab0ee5b1c8ebc74ba (diff) | |
| download | talos-obmc-uboot-fb95169e39f2d03270bed552d27bbb02627a443e.tar.gz talos-obmc-uboot-fb95169e39f2d03270bed552d27bbb02627a443e.zip | |
ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling
This patch merges the ECC handling (ECC parity byte writing) into one
file (ecc.c) for all PPC4xx SDRAM controllers except for PPC440EPx/GRx.
This exception is because only those PPC's use the completely different
Denali SDRAM controller core.
Previously we had two routines to generate/write the ECC parity bytes.
With this patch we now only have one core function left.
Tested on Kilauea (no ECC) and Katmai (with and without ECC).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Felix Radensky <felix@embedded-sol.com>
Cc: Grant Erickson <gerickson@nuovations.com>
Cc: Pieter Voorthuijsen <pv@prodrive.nl>
Diffstat (limited to 'cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c')
| -rw-r--r-- | cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 91bf582d6e..0283c91d84 100644 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -42,6 +42,8 @@ #include <asm/io.h> #include <asm/processor.h> +#include "ecc.h" + #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) /* @@ -177,7 +179,7 @@ static u32 *get_membase(int bxcr_num) static inline void ecc_clear_status_reg(void) { - mtsdram(SDRAM_ECCCR, 0xffffffff); + mtsdram(SDRAM_ECCES, 0xffffffff); #if defined(SDRAM_R0BAS) mtdcr(SDRAM_ERRSTATLL, 0xffffffff); #endif @@ -210,7 +212,7 @@ static int ecc_check_status_reg(void) * ecc error, then don't count * this as a passing value */ - mfsdram(SDRAM_ECCCR, ecc_status); + mfsdram(SDRAM_ECCES, ecc_status); if (ecc_status != 0x00000000) { /* clear on error */ ecc_clear_status_reg(); |
