summaryrefslogtreecommitdiffstats
path: root/cpu/mpc8xxx
diff options
context:
space:
mode:
authorDave Liu <daveliu@freescale.com>2009-11-12 07:26:37 +0800
committerKumar Gala <galak@kernel.crashing.org>2009-11-12 08:09:49 -0600
commit3ad95deb30ac73bd57e966d321215a17d3236f9f (patch)
tree342daf9b3dfaa0998ae2c1b562a48eb68b407538 /cpu/mpc8xxx
parent4f127980e0d4ba179b4628ebf8e8642210731055 (diff)
downloadtalos-obmc-uboot-3ad95deb30ac73bd57e966d321215a17d3236f9f.tar.gz
talos-obmc-uboot-3ad95deb30ac73bd57e966d321215a17d3236f9f.zip
fsl-ddr: Fix the chip-select interleaving issue
commit 1542fbdeec0d1e2a6df13189df8dcb1ce8802be3 introduced one new bug to chip-select interleaving. Single DDR controller also can do the chip-select interleaving if there is dual-rank or qual-rank DIMMs. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc8xxx')
-rw-r--r--cpu/mpc8xxx/ddr/options.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index db442918e9..2e030c11a3 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -22,9 +22,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
unsigned int ctrl_num)
{
unsigned int i;
-#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
const char *p;
-#endif
/* Chip select options. */
@@ -242,8 +240,10 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
simple_strtoul(p, NULL, 0);
}
}
+#endif
- if( (p = getenv("ba_intlv_ctl")) != NULL) {
+ if( ((p = getenv("ba_intlv_ctl")) != NULL) &&
+ (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
if (strcmp(p, "cs0_cs1") == 0)
popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
else if (strcmp(p, "cs2_cs3") == 0)
@@ -283,7 +283,6 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
break;
}
}
-#endif
fsl_ddr_board_options(popts, pdimm, ctrl_num);
OpenPOWER on IntegriCloud