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authorHeiko Schocher <hs@denx.de>2013-08-19 16:38:56 +0200
committerTom Rini <trini@ti.com>2013-08-28 11:44:59 -0400
commitdafd4db33a99f05616f02283f6fd3ba065278dcb (patch)
tree7f636b99e8139870aaa0ae31b12eb0ea2a458fb7 /board
parent457bb50560c983fc69090dad1fb16b128e88a520 (diff)
downloadtalos-obmc-uboot-dafd4db33a99f05616f02283f6fd3ba065278dcb.tar.gz
talos-obmc-uboot-dafd4db33a99f05616f02283f6fd3ba065278dcb.zip
arm, am33xx: add defines for gmii_sel_register bits
Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Diffstat (limited to 'board')
-rw-r--r--board/isee/igep0033/board.c6
-rw-r--r--board/phytec/pcm051/board.c2
-rw-r--r--board/ti/am335x/board.c6
3 files changed, 3 insertions, 11 deletions
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index a24c22b1ad..9e91f68eb0 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -27,9 +27,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* MII mode defines */
-#define RMII_MODE_ENABLE 0x4D
-
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifdef CONFIG_SPL_BUILD
@@ -158,7 +155,8 @@ int board_eth_init(bd_t *bis)
eth_setenv_enetaddr("ethaddr", mac_addr);
}
- writel(RMII_MODE_ENABLE, &cdev->miisel);
+ writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
+ &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index f53c5bbd4b..e40b0bd44d 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -31,8 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
/* MII mode defines */
-#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0xA
#define RMII_RGMII2_MODE_ENABLE 0x49
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 04c37e2db6..cc0442612f 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -30,10 +30,6 @@
DECLARE_GLOBAL_DATA_PTR;
-/* MII mode defines */
-#define MII_MODE_ENABLE 0x0
-#define RGMII_MODE_ENABLE 0x3A
-
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
@@ -460,7 +456,7 @@ int board_eth_init(bd_t *bis)
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_MII;
} else {
- writel(RGMII_MODE_ENABLE, &cdev->miisel);
+ writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
PHY_INTERFACE_MODE_RGMII;
}
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