path: root/board
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authorAlexey Brodkin <>2016-06-08 08:19:33 +0300
committerAlexey Brodkin <>2016-06-13 14:38:05 +0200
commitc7d8db66ffd1c20b6a27445af892c28305e64e8a (patch)
tree8b74ac2b269a23f64b3aec13ecff6aa6d1d9ee4a /board
parenta4a43fcf9cca1ebd3d26f9a01b923b7393d69c54 (diff)
board: axs10x: Flush entire cache after programming reset vector
Now when we have support of IOC (IO-Coherency block) cahce operations on regions are tuned to not be dummy stubs if IOC was found and enabled in the core. That makes flush_dcache_range() useless for our purposes here. And since we do need to flush modified reset vector to at least L2 cache (AKA SLC) so other cores will see it via its L1 instruction cache we're using always functional flush_dcache_all() here. Signed-off-by: Alexey Brodkin <> Cc: Marek Vasut <>
Diffstat (limited to 'board')
1 files changed, 1 insertions, 1 deletions
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
index 84ee2bf43d..a5e774b2cf 100644
--- a/board/synopsys/axs101/axs101.c
+++ b/board/synopsys/axs101/axs101.c
@@ -54,7 +54,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
/* Make sure other cores see written value in memory */
- flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
+ flush_dcache_all();
void smp_kick_all_cpus(void)
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