path: root/board
diff options
authorAkshay Bhat <>2016-04-12 18:14:00 -0400
committerStefano Babic <>2016-04-19 16:05:51 +0200
commit8d293f49b419dd394cdf4b7a501ad86b782efc3f (patch)
tree3e6d33d2285b3e68a77a3dc96cb39c1941ad3c3a /board
parent54971ac6de20b8834882efb69dc6ad5c1d4a9915 (diff)
board: ge: bx50v3: Fix to meet LVDS display power on timing
On a reset/reboot, the display power needs to be off for atleast 500ms before turning it back on. So add a delay to the boot process to meet the display timing requirement. Signed-off-by: Akshay Bhat <> Cc: Stefano Babic <>
Diffstat (limited to 'board')
1 files changed, 7 insertions, 0 deletions
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index dcf51dd7d0..ff8f4d7b97 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -476,6 +476,13 @@ static void setup_display_bx50v3(void)
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ /* When a reset/reboot is performed the display power needs to be turned
+ * off for atleast 500ms. The boot time is ~300ms, we need to wait for
+ * an additional 200ms here. Unfortunately we use external PMIC for
+ * doing the reset, so can not differentiate between POR vs soft reset
+ */
+ mdelay(200);
/* IPU1 DI0 clock is 480/7 = 68.5 MHz */
setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
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