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authorSimon Glass <sjg@chromium.org>2016-03-16 07:44:43 -0600
committerBin Meng <bmeng.cn@gmail.com>2016-03-17 10:27:27 +0800
commit374e78efb0c6739c8c700325acca769d7a9e47de (patch)
tree4e626abc6d6bd43beec4b8bdad9025b4ef0e08e7 /board
parente5aa8a9b1593f524af07318d4e84352b06a53402 (diff)
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x86: Add support for the samus chromebook
This adds basic support for chromebook_samus. This is the 2015 Pixel and is based on an Intel broadwell platform. Supported so far are: - Serial - SPI flash - SDRAM init (with MRC cache) - SATA - Video (on the internal LCD panel) - Keyboard Various less-visible drivers are provided to make the above work (e.g. PCH, power control and LPC). The platform requires various binary blobs which are documented in the README. The major missing feature is USB3 since the existing U-Boot support does not work correctly with Intel XHCI controllers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'board')
-rw-r--r--board/google/Kconfig13
-rw-r--r--board/google/chromebook_samus/Kconfig40
-rw-r--r--board/google/chromebook_samus/MAINTAINERS6
-rw-r--r--board/google/chromebook_samus/Makefile7
-rw-r--r--board/google/chromebook_samus/samus.c18
5 files changed, 84 insertions, 0 deletions
diff --git a/board/google/Kconfig b/board/google/Kconfig
index e9559c9080..7ba73a2461 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -36,9 +36,22 @@ config TARGET_CHROMEBOX_PANTHER
video output and a 16GB SATA solid state drive. There is no Chrome
OS EC on this model.
+config TARGET_CHROMEBOOK_SAMUS
+ bool "Chromebook samus"
+ help
+ This is the Chromebook Pixel released in 2015. It uses an Intel
+ Broadwell U Core i5 or Core i7 CPU with either 8GB or 16GB of
+ LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
+ 720p webcam, USB SD reader, microphone and speakers, 2 USB 3 Type
+ C ports which can support charging and up to a 4K external display.
+ There is a solid state drive, either 32GB or 64GB. There is a
+ Chrome OS EC connected on LPC, and it provides a 2560x1700 high
+ resolution touch-enabled LCD display.
+
endchoice
source "board/google/chromebook_link/Kconfig"
source "board/google/chromebox_panther/Kconfig"
+source "board/google/chromebook_samus/Kconfig"
endif
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
new file mode 100644
index 0000000000..f2b9481563
--- /dev/null
+++ b/board/google/chromebook_samus/Kconfig
@@ -0,0 +1,40 @@
+if TARGET_CHROMEBOOK_SAMUS
+
+config SYS_BOARD
+ default "chromebook_samus"
+
+config SYS_VENDOR
+ default "google"
+
+config SYS_SOC
+ default "broadwell"
+
+config SYS_CONFIG_NAME
+ default "chromebook_samus"
+
+config SYS_TEXT_BASE
+ default 0xffe00000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select X86_RESET_VECTOR
+ select INTEL_BROADWELL
+ select HAVE_INTEL_ME
+ select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+ default 0xf0000000
+
+config EARLY_POST_CROS_EC
+ bool "Enable early post to Chrome OS EC"
+ default y
+
+config SYS_CAR_ADDR
+ hex
+ default 0xff7c0000
+
+config SYS_CAR_SIZE
+ hex
+ default 0x40000
+
+endif
diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS
new file mode 100644
index 0000000000..5500e46b40
--- /dev/null
+++ b/board/google/chromebook_samus/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK SAMUS BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/google/chromebook_samus/
+F: include/configs/chromebook_samus.h
+F: configs/chromebook_samus_defconfig
diff --git a/board/google/chromebook_samus/Makefile b/board/google/chromebook_samus/Makefile
new file mode 100644
index 0000000000..152228678b
--- /dev/null
+++ b/board/google/chromebook_samus/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += samus.o
diff --git a/board/google/chromebook_samus/samus.c b/board/google/chromebook_samus/samus.c
new file mode 100644
index 0000000000..3c3f5d4833
--- /dev/null
+++ b/board/google/chromebook_samus/samus.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+
+int arch_early_init_r(void)
+{
+ return cpu_run_reference_code();
+}
+
+int board_early_init_f(void)
+{
+ return 0;
+}
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