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| author | shengjiangwu <shengjiangwu@icloud.com> | 2015-12-22 17:18:09 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-12-22 21:30:02 +0100 |
| commit | caee45ecc32329294d0f42a54b5c47794ecbe750 (patch) | |
| tree | 915f8c8e48813ed124f69b12fddf8b498f90cca6 /board | |
| parent | b0808b912d3f728597afcb97545d89b9f34dbc3f (diff) | |
| download | talos-obmc-uboot-caee45ecc32329294d0f42a54b5c47794ecbe750.tar.gz talos-obmc-uboot-caee45ecc32329294d0f42a54b5c47794ecbe750.zip | |
arm: socfpga: Fix QSPI doesn't work on socdk board
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.
Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board')
| -rw-r--r-- | board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 | ||||
| -rw-r--r-- | board/altera/cyclone5-socdk/qts/pll_config.h | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index 442b1e0862..06783dcd80 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = { 2, /* MIXED1IO12 */ 2, /* MIXED1IO13 */ 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ 0, /* MIXED1IO21 */ 0, /* MIXED2IO0 */ 0, /* MIXED2IO1 */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 9e336e3e81..4abd2e0aac 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -14,7 +14,7 @@ #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 |
