Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

43 files changed, 1400 insertions, 124 deletions

diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index 6b8af14e7a..f1bed51d30 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -7,7 +7,12 @@
 #include <common.h>
 #include <command.h>
 #include <i2c.h>
+#include <asm/io.h>
+#ifdef CONFIG_LS1043A
+#include <asm/arch/immap_lsch2.h>
+#else
 #include <asm/immap_85xx.h>
+#endif
 #include "vid.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -240,7 +245,11 @@ static int set_voltage_to_IR(int i2caddress, int vdd)
 	 * SoC before converting into an IR VID value
 	 */
 	vdd += board_vdd_drop_compensation();
+#ifdef CONFIG_LS1043A
+	vid = DIV_ROUND_UP(vdd - 265, 5);
+#else
 	vid = DIV_ROUND_UP(vdd - 245, 5);
+#endif
 
 	ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
 			1, (void *)&vid, sizeof(vid));
@@ -276,8 +285,12 @@ static int set_voltage(int i2caddress, int vdd)
 int adjust_vdd(ulong vdd_override)
 {
 	int re_enable = disable_interrupts();
+#ifdef CONFIG_LS1043A
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#else
 	ccsr_gur_t __iomem *gur =
 		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
 	u32 fusesr;
 	u8 vid;
 	int vdd_target, vdd_current, vdd_last;
@@ -352,12 +365,21 @@ int adjust_vdd(ulong vdd_override)
 	 * | T |          |         |                 |         |
 	 * ------------------------------------------------------
 	 */
+#ifdef CONFIG_LS1043A
+	vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
+		FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
+	if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
+		vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
+			FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
+	}
+#else
 	vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
 		FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
 	if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
 		vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
 			FSL_CORENET_DCFG_FUSESR_VID_MASK;
 	}
+#endif
 	vdd_target = vdd[vid];
 
 	/* check override variable for overriding VDD */
diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig
new file mode 100644
index 0000000000..7e27f8f5b1
--- /dev/null
+++ b/board/freescale/ls1043aqds/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1043AQDS
+
+config SYS_BOARD
+	default "ls1043aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1043aqds"
+
+endif
diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS
new file mode 100644
index 0000000000..0c7f648b6c
--- /dev/null
+++ b/board/freescale/ls1043aqds/MAINTAINERS
@@ -0,0 +1,9 @@
+LS1043AQDS BOARD
+M:	Mingkai Hu <Mingkai.Hu@freescale.com>
+S:	Maintained
+F:	board/freescale/ls1043aqds/
+F:	include/configs/ls1043aqds.h
+F:	configs/ls1043aqds_defconfig
+F:	configs/ls1043aqds_nor_ddr3_defconfig
+F:	configs/ls1043aqds_nand_defconfig
+F:	configs/ls1043aqds_sdcard_ifc_defconfig
diff --git a/board/freescale/ls1043aqds/Makefile b/board/freescale/ls1043aqds/Makefile
new file mode 100644
index 0000000000..f727bfd622
--- /dev/null
+++ b/board/freescale/ls1043aqds/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ddr.o
+obj-y += eth.o
+obj-y += ls1043aqds.o
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
new file mode 100644
index 0000000000..6261a778aa
--- /dev/null
+++ b/board/freescale/ls1043aqds/README
@@ -0,0 +1,96 @@
+Overview
+--------
+The LS1043A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS1043A
+LayerScape Architecture processor. The LS1043AQDS provides SW development
+platform for the Freescale LS1043A processor series, with a complete
+debugging environment.
+
+LS1043A SoC Overview
+--------------------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+     management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+   - Up to 1 x XFI supporting 10G interface
+   - Up to 1 x QSGMII
+   - Up to 4 x SGMII supporting 1000Mbps
+   - Up to 2 x SGMII supporting 2500Mbps
+   - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+   - Three PCIe 2.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+ LS1043AQDS board Overview
+ -----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - QSGMII
+      - SATA 3.0
+      - XFI
+ - DDR Controller
+     - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
+ -IFC/Local Bus
+    - One in-socket 128 MB NOR flash 16-bit data bus
+    - One 512 MB NAND flash with ECC support
+    - PromJet Port
+    - FPGA connection
+ - USB 3.0
+    - Three high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - The other two USB 3.0 ports configured as OTG with micro-AB connector
+ - SDHC port connects directly to an adapter card slot, featuring:
+    - Optional clock feedback paths, and optional high-speed voltage translation assistance
+    - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
+    - eMMC memory devices
+ - DSPI: Onboard support for three SPI flash memory devices
+ - 4 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - Two 4-pin serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+Start Address	End Address	Description		Size
+0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM		1MB
+0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR			240MB
+0x00_1000_0000	0x00_1000_FFFF	OCRAM0			64KB
+0x00_1001_0000	0x00_1001_FFFF	OCRAM1			64KB
+0x00_2000_0000	0x00_20FF_FFFF	DCSR			16MB
+0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash		128MB
+0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash	64KB
+0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA		4KB
+0x00_8000_0000	0x00_FFFF_FFFF	DRAM1			2GB
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
new file mode 100644
index 0000000000..705e3843f4
--- /dev/null
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#ifdef CONFIG_FSL_DEEP_SLEEP
+#include <fsl_sleep.h>
+#endif
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 3) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+	/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->cpo_override = pbsp->cpo_override;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found for %lu MT/s\n",
+		       ddr_freq);
+		printf("Trying to use the highest speed (%u) parameters\n",
+		       pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
+	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
+
+	/* force DDR bus width to 32 bits */
+	popts->data_bus_width = 1;
+	popts->otf_burst_chop_en = 0;
+	popts->burst_length = DDR_BL8;
+	popts->bstopre = 0;		/* enable auto precharge */
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 1;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+#ifdef CONFIG_SYS_FSL_DDR4
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+			  DDR_CDR2_VREF_OVRD(70);	/* Vref = 70% */
+#else
+	popts->cswl_override = DDR_CSWL_CS0;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	return fsl_ddr_sdram_size();
+#else
+	puts("Initializing DDR....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+#endif
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+	fsl_dp_ddr_restore();
+#endif
+
+	return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h
new file mode 100644
index 0000000000..8adb660012
--- /dev/null
+++ b/board/freescale/ls1043aqds/ddr.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 rank_gb;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo_override;
+	u32 write_data_delay;
+	u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+#ifdef CONFIG_SYS_FSL_DDR4
+	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E0A,},
+	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+#elif defined(CONFIG_SYS_FSL_DDR3)
+	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+#else
+#error DDR type not defined
+#endif
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+#endif
diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c
new file mode 100644
index 0000000000..b7fc360e2c
--- /dev/null
+++ b/board/freescale/ls1043aqds/eth.c
@@ -0,0 +1,492 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <fsl_dtsec.h>
+#include <malloc.h>
+#include <asm/arch/fsl_serdes.h>
+
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "ls1043aqds_qixis.h"
+
+#define EMI_NONE	0xFF
+#define EMI1_RGMII1	0
+#define EMI1_RGMII2	1
+#define EMI1_SLOT1	2
+#define EMI1_SLOT2	3
+#define EMI1_SLOT3	4
+#define EMI1_SLOT4	5
+#define EMI2		6
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+	"LS1043AQDS_MDIO_RGMII1",
+	"LS1043AQDS_MDIO_RGMII2",
+	"LS1043AQDS_MDIO_SLOT1",
+	"LS1043AQDS_MDIO_SLOT2",
+	"LS1043AQDS_MDIO_SLOT3",
+	"LS1043AQDS_MDIO_SLOT4",
+	"NULL",
+};
+
+/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
+static u8 lane_to_slot[] = {1, 2, 3, 4};
+
+static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
+{
+	return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+	struct mii_dev *bus;
+	const char *name;
+
+	if (muxval > EMI2)
+		return NULL;
+
+	name = ls1043aqds_mdio_name_for_muxval(muxval);
+
+	if (!name) {
+		printf("No bus for muxval %x\n", muxval);
+		return NULL;
+	}
+
+	bus = miiphy_get_dev_by_name(name);
+
+	if (!bus) {
+		printf("No bus by name %s\n", name);
+		return NULL;
+	}
+
+	return bus;
+}
+
+struct ls1043aqds_mdio {
+	u8 muxval;
+	struct mii_dev *realbus;
+};
+
+static void ls1043aqds_mux_mdio(u8 muxval)
+{
+	u8 brdcfg4;
+
+	if (muxval < 7) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+		brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+		QIXIS_WRITE(brdcfg[4], brdcfg4);
+	}
+}
+
+static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
+			      int regnum)
+{
+	struct ls1043aqds_mdio *priv = bus->priv;
+
+	ls1043aqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
+			       int regnum, u16 value)
+{
+	struct ls1043aqds_mdio *priv = bus->priv;
+
+	ls1043aqds_mux_mdio(priv->muxval);
+
+	return priv->realbus->write(priv->realbus, addr, devad,
+				    regnum, value);
+}
+
+static int ls1043aqds_mdio_reset(struct mii_dev *bus)
+{
+	struct ls1043aqds_mdio *priv = bus->priv;
+
+	return priv->realbus->reset(priv->realbus);
+}
+
+static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
+{
+	struct ls1043aqds_mdio *pmdio;
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus) {
+		printf("Failed to allocate ls1043aqds MDIO bus\n");
+		return -1;
+	}
+
+	pmdio = malloc(sizeof(*pmdio));
+	if (!pmdio) {
+		printf("Failed to allocate ls1043aqds private data\n");
+		free(bus);
+		return -1;
+	}
+
+	bus->read = ls1043aqds_mdio_read;
+	bus->write = ls1043aqds_mdio_write;
+	bus->reset = ls1043aqds_mdio_reset;
+	sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
+
+	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+	if (!pmdio->realbus) {
+		printf("No bus with name %s\n", realbusname);
+		free(bus);
+		free(pmdio);
+		return -1;
+	}
+
+	pmdio->muxval = muxval;
+	bus->priv = pmdio;
+	return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+			      enum fm_port port, int offset)
+{
+	struct fixed_link f_link;
+
+	if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+		if (port == FM1_DTSEC9) {
+			fdt_set_phy_handle(fdt, compat, addr,
+					   "sgmii_riser_s1_p1");
+		} else if (port == FM1_DTSEC2) {
+			fdt_set_phy_handle(fdt, compat, addr,
+					   "sgmii_riser_s2_p1");
+		} else if (port == FM1_DTSEC5) {
+			fdt_set_phy_handle(fdt, compat, addr,
+					   "sgmii_riser_s3_p1");
+		} else if (port == FM1_DTSEC6) {
+			fdt_set_phy_handle(fdt, compat, addr,
+					   "sgmii_riser_s4_p1");
+		}
+	} else if (fm_info_get_enet_if(port) ==
+		   PHY_INTERFACE_MODE_SGMII_2500) {
+		/* 2.5G SGMII interface */
+		f_link.phy_id = port;
+		f_link.duplex = 1;
+		f_link.link_speed = 1000;
+		f_link.pause = 0;
+		f_link.asym_pause = 0;
+		/* no PHY for 2.5G SGMII */
+		fdt_delprop(fdt, offset, "phy-handle");
+		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+		fdt_setprop_string(fdt, offset, "phy-connection-type",
+				   "sgmii-2500");
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
+		switch (mdio_mux[port]) {
+		case EMI1_SLOT1:
+			switch (port) {
+			case FM1_DTSEC1:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii_s1_p1");
+				break;
+			case FM1_DTSEC2:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii_s1_p2");
+				break;
+			case FM1_DTSEC5:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii_s1_p3");
+				break;
+			case FM1_DTSEC6:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii_s1_p4");
+				break;
+			default:
+				break;
+			}
+			break;
+		case EMI1_SLOT2:
+			switch (port) {
+			case FM1_DTSEC1:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii_s2_p1");
+				break;
+			case FM1_DTSEC2:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii_s2_p2");
+				break;
+			case FM1_DTSEC5:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii_s2_p3");
+				break;
+			case FM1_DTSEC6:
+				fdt_set_phy_handle(fdt, compat, addr,
+						   "qsgmii_s2_p4");
+				break;
+			default:
+				break;
+			}
+			break;
+		default:
+			break;
+		}
+		fdt_delprop(fdt, offset, "phy-connection-type");
+		fdt_setprop_string(fdt, offset, "phy-connection-type",
+				   "qsgmii");
+	} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
+		   port == FM1_10GEC1) {
+		/* XFI interface */
+		f_link.phy_id = port;
+		f_link.duplex = 1;
+		f_link.link_speed = 10000;
+		f_link.pause = 0;
+		f_link.asym_pause = 0;
+		/* no PHY for XFI */
+		fdt_delprop(fdt, offset, "phy-handle");
+		fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
+		fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
+	}
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int i;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+		case PHY_INTERFACE_MODE_QSGMII:
+			switch (mdio_mux[i]) {
+			case EMI1_SLOT1:
+				fdt_status_okay_by_alias(fdt, "emi1_slot1");
+				break;
+			case EMI1_SLOT2:
+				fdt_status_okay_by_alias(fdt, "emi1_slot2");
+				break;
+			case EMI1_SLOT3:
+				fdt_status_okay_by_alias(fdt, "emi1_slot3");
+				break;
+			case EMI1_SLOT4:
+				fdt_status_okay_by_alias(fdt, "emi1_slot4");
+				break;
+			default:
+				break;
+			}
+			break;
+		case PHY_INTERFACE_MODE_XGMII:
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	int i, idx, lane, slot, interface;
+	struct memac_mdio_info dtsec_mdio_info;
+	struct memac_mdio_info tgec_mdio_info;
+	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 srds_s1;
+
+	srds_s1 = in_be32(&gur->rcwsr[4]) &
+			FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+	srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+	/* Initialize the mdio_mux array so we can recognize empty elements */
+	for (i = 0; i < NUM_FM_PORTS; i++)
+		mdio_mux[i] = EMI_NONE;
+
+	dtsec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the 1G MDIO bus */
+	fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+	tgec_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+	/* Register the muxing front-ends to the MDIO buses */
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+	ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+	ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+	/* Set the two on-board RGMII PHY address */
+	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+
+	switch (srds_s1) {
+	case 0x2555:
+		/* 2.5G SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, 9);
+		break;
+	case 0x4555:
+	case 0x4558:
+		/* QSGMII on lane A, MAC 1/2/5/6 */
+		fm_info_set_phy_address(FM1_DTSEC1,
+					QSGMII_CARD_PORT1_PHY_ADDR_S1);
+		fm_info_set_phy_address(FM1_DTSEC2,
+					QSGMII_CARD_PORT2_PHY_ADDR_S1);
+		fm_info_set_phy_address(FM1_DTSEC5,
+					QSGMII_CARD_PORT3_PHY_ADDR_S1);
+		fm_info_set_phy_address(FM1_DTSEC6,
+					QSGMII_CARD_PORT4_PHY_ADDR_S1);
+		break;
+	case 0x1355:
+		/* SGMII on lane B, MAC 2*/
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+		break;
+	case 0x2355:
+		/* 2.5G SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, 9);
+		/* SGMII on lane B, MAC 2*/
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+		break;
+	case 0x3335:
+		/* SGMII on lane C, MAC 5 */
+		fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
+	case 0x3355:
+	case 0x3358:
+		/* SGMII on lane B, MAC 2 */
+		fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
+	case 0x3555:
+	case 0x3558:
+		/* SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+		break;
+	case 0x1455:
+		/* QSGMII on lane B, MAC 1/2/5/6 */
+		fm_info_set_phy_address(FM1_DTSEC1,
+					QSGMII_CARD_PORT1_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC2,
+					QSGMII_CARD_PORT2_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC5,
+					QSGMII_CARD_PORT3_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC6,
+					QSGMII_CARD_PORT4_PHY_ADDR_S2);
+		break;
+	case 0x2455:
+		/* 2.5G SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, 9);
+		/* QSGMII on lane B, MAC 1/2/5/6 */
+		fm_info_set_phy_address(FM1_DTSEC1,
+					QSGMII_CARD_PORT1_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC2,
+					QSGMII_CARD_PORT2_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC5,
+					QSGMII_CARD_PORT3_PHY_ADDR_S2);
+		fm_info_set_phy_address(FM1_DTSEC6,
+					QSGMII_CARD_PORT4_PHY_ADDR_S2);
+		break;
+	case 0x2255:
+		/* 2.5G SGMII on lane A, MAC 9 */
+		fm_info_set_phy_address(FM1_DTSEC9, 9);
+		/* 2.5G SGMII on lane B, MAC 2 */
+		fm_info_set_phy_address(FM1_DTSEC2, 2);
+		break;
+	case 0x3333:
+		/* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
+		fm_info_set_phy_address(FM1_DTSEC9,
+					SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2,
+					SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC5,
+					SGMII_CARD_PORT1_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6,
+					SGMII_CARD_PORT1_PHY_ADDR);
+		break;
+	default:
+		printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
+		       srds_s1);
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		interface = fm_info_get_enet_if(i);
+		switch (interface) {
+		case PHY_INTERFACE_MODE_SGMII:
+		case PHY_INTERFACE_MODE_SGMII_2500:
+		case PHY_INTERFACE_MODE_QSGMII:
+			if (interface == PHY_INTERFACE_MODE_SGMII) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						SGMII_FM1_DTSEC1 + idx);
+			} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						SGMII_2500_FM1_DTSEC1 + idx);
+			} else {
+				lane = serdes_get_first_lane(FSL_SRDS_1,
+						QSGMII_FM1_A);
+			}
+
+			if (lane < 0)
+				break;
+
+			slot = lane_to_slot[lane];
+			debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+			      idx + 1, slot);
+			if (QIXIS_READ(present2) & (1 << (slot - 1)))
+				fm_disable_port(i);
+
+			switch (slot) {
+			case 1:
+				mdio_mux[i] = EMI1_SLOT1;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 2:
+				mdio_mux[i] = EMI1_SLOT2;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 3:
+				mdio_mux[i] = EMI1_SLOT3;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			case 4:
+				mdio_mux[i] = EMI1_SLOT4;
+				fm_info_set_mdio(i, mii_dev_for_muxval(
+						 mdio_mux[i]));
+				break;
+			default:
+				break;
+			}
+			break;
+		case PHY_INTERFACE_MODE_RGMII:
+			if (i == FM1_DTSEC3)
+				mdio_mux[i] = EMI1_RGMII1;
+			else if (i == FM1_DTSEC4)
+				mdio_mux[i] = EMI1_RGMII2;
+			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+			break;
+		default:
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+	return pci_eth_init(bis);
+}
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
new file mode 100644
index 0000000000..d6696ca812
--- /dev/null
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -0,0 +1,333 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_ifc.h>
+#include <spl.h>
+
+#include "../common/qixis.h"
+#include "ls1043aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	MUX_TYPE_GPIO,
+};
+
+/* LS1043AQDS serdes mux */
+#define CFG_SD_MUX1_SLOT2	0x0 /* SLOT2 TX/RX0 */
+#define CFG_SD_MUX1_SLOT1	0x1 /* SLOT1 TX/RX1 */
+#define CFG_SD_MUX2_SLOT3	0x0 /* SLOT3 TX/RX0 */
+#define CFG_SD_MUX2_SLOT1	0x1 /* SLOT1 TX/RX2 */
+#define CFG_SD_MUX3_SLOT4	0x0 /* SLOT4 TX/RX0 */
+#define CFG_SD_MUX3_MUX4	0x1 /* MUX4 */
+#define CFG_SD_MUX4_SLOT3	0x0 /* SLOT3 TX/RX1 */
+#define CFG_SD_MUX4_SLOT1	0x1 /* SLOT1 TX/RX3 */
+
+int checkboard(void)
+{
+	char buf[64];
+#ifndef CONFIG_SD_BOOT
+	u8 sw;
+#endif
+
+	puts("Board: LS1043AQDS, boot from ");
+
+#ifdef CONFIG_SD_BOOT
+	puts("SD\n");
+#else
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw == 0x8)
+		puts("PromJet\n");
+	else if (sw == 0x9)
+		puts("NAND\n");
+	else if (sw == 0x15)
+		printf("IFCCard\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+#endif
+
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
+	       QIXIS_READ(id), QIXIS_READ(arch));
+
+	printf("FPGA:  v%d (%s), build %d\n",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+
+	return 0;
+}
+
+bool if_board_diff_clk(void)
+{
+	u8 diff_conf = QIXIS_READ(brdcfg[11]);
+
+	return diff_conf & 0x40;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0f) {
+	case QIXIS_SYSCLK_64:
+		return 64000000;
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	if (if_board_diff_clk())
+		return get_board_sys_clk();
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+
+	return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+	int ret;
+
+	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+	if (ret) {
+		puts("PCA: failed to select proper channel\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	/*
+	 * When resuming from deep sleep, the I2C channel may not be
+	 * in the default channel. So, switch to the default channel
+	 * before accessing DDR SPD.
+	 */
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	gd->ram_size = initdram(0);
+
+	return 0;
+}
+
+int i2c_multiplexer_select_vid_channel(u8 channel)
+{
+	return select_i2c_ch_pca9547(channel);
+}
+
+void board_retimer_init(void)
+{
+	u8 reg;
+
+	/* Retimer is connected to I2C1_CH7_CH5 */
+	reg = I2C_MUX_CH7;
+	i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
+	reg = I2C_MUX_CH5;
+	i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
+
+	/* Access to Control/Shared register */
+	reg = 0x0;
+	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+
+	/* Read device revision and ID */
+	i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
+	debug("Retimer version id = 0x%x\n", reg);
+
+	/* Enable Broadcast. All writes target all channel register sets */
+	reg = 0x0c;
+	i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
+
+	/* Reset Channel Registers */
+	i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+	reg |= 0x4;
+	i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
+
+	/* Enable override divider select and Enable Override Output Mux */
+	i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
+	reg |= 0x24;
+	i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
+
+	/* Select VCO Divider to full rate (000) */
+	i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
+	reg &= 0x8f;
+	i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
+
+	/* Selects active PFD MUX Input as Re-timed Data (001) */
+	i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
+	reg &= 0x3f;
+	reg |= 0x20;
+	i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
+
+	/* Set data rate as 10.3125 Gbps */
+	reg = 0x0;
+	i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
+	reg = 0xb2;
+	i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
+	reg = 0x90;
+	i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
+	reg = 0xb3;
+	i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
+	reg = 0xcd;
+	i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_DEEP_SLEEP
+/* determine if it is a warm boot */
+bool is_warm_boot(void)
+{
+#define DCFG_CCSR_CRSTSR_WDRFR	(1 << 3)
+	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+	if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
+		return 1;
+
+	return 0;
+}
+#endif
+
+int config_board_mux(int ctrl_type)
+{
+	u8 reg14;
+
+	reg14 = QIXIS_READ(brdcfg[14]);
+
+	switch (ctrl_type) {
+	case MUX_TYPE_GPIO:
+		reg14 = (reg14 & (~0x30)) | 0x20;
+		break;
+	default:
+		puts("Unsupported mux interface type\n");
+		return -1;
+	}
+
+	QIXIS_WRITE(brdcfg[14], reg14);
+
+	return 0;
+}
+
+int config_serdes_mux(void)
+{
+	return 0;
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	if (hwconfig("gpio"))
+		config_board_mux(MUX_TYPE_GPIO);
+
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+				   CONFIG_SYS_CCI400_ADDR;
+
+	/* Set CCI-400 control override register to enable barrier
+	 * transaction */
+	out_le32(&cci->ctrl_ord,
+		 CCI400_CTRLORD_EN_BARRIER);
+
+	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+	board_retimer_init();
+
+#ifdef CONFIG_SYS_FSL_SERDES
+	config_serdes_mux();
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+	return 0;
+}
+#endif
+
+u8 flash_read8(void *addr)
+{
+	return __raw_readb(addr + 1);
+}
+
+void flash_write16(u16 val, void *addr)
+{
+	u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
+
+	__raw_writew(shftval, addr);
+}
+
+u16 flash_read16(void *addr)
+{
+	u16 val = __raw_readw(addr);
+
+	return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
+}
diff --git a/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
new file mode 100644
index 0000000000..f072274f47
--- /dev/null
+++ b/board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
@@ -0,0 +1,14 @@
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff
diff --git a/board/freescale/ls1043aqds/ls1043aqds_qixis.h b/board/freescale/ls1043aqds/ls1043aqds_qixis.h
new file mode 100644
index 0000000000..8783be8927
--- /dev/null
+++ b/board/freescale/ls1043aqds/ls1043aqds_qixis.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+#define QIXIS_SYSCLK_64			0x8
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif
diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
new file mode 100644
index 0000000000..935ffc0102
--- /dev/null
+++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0810000f 0c000000 00000000 00000000
+14550002 80004012 e0106000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
new file mode 100644
index 0000000000..17a5dd0259
--- /dev/null
+++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# RCW
+# Enable IFC; disable QSPI
+0810000f 0c000000 00000000 00000000
+14550002 80004012 60040000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index 9032ed36c8..cdd50d6d18 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -69,7 +69,23 @@ int dram_init(void)
 
 int board_early_init_f(void)
 {
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+	u32 usb_pwrfault;
+
 	fsl_lsch2_early_init_f();
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+	out_be32(&scfg->rcwpmuxcr0, 0x3333);
+	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+	usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB3_SHIFT) |
+			(SCFG_USBPWRFAULT_DEDICATED <<
+			SCFG_USBPWRFAULT_USB2_SHIFT) |
+			(SCFG_USBPWRFAULT_SHARED <<
+			 SCFG_USBPWRFAULT_USB1_SHIFT);
+	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/ls2085a/Kconfig b/board/freescale/ls2080a/Kconfig
index 042f85b367..0b938ffb54 100644
--- a/board/freescale/ls2085a/Kconfig
+++ b/board/freescale/ls2080a/Kconfig
@@ -1,7 +1,7 @@
-if TARGET_LS2085A_EMU
+if TARGET_LS2080A_EMU
 
 config SYS_BOARD
-	default "ls2085a"
+	default "ls2080a"
 
 config SYS_VENDOR
 	default "freescale"
@@ -10,14 +10,14 @@ config SYS_SOC
 	default "fsl-layerscape"
 
 config SYS_CONFIG_NAME
-	default "ls2085a_emu"
+	default "ls2080a_emu"
 
 endif
 
-if TARGET_LS2085A_SIMU
+if TARGET_LS2080A_SIMU
 
 config SYS_BOARD
-	default "ls2085a"
+	default "ls2080a"
 
 config SYS_VENDOR
 	default "freescale"
@@ -26,6 +26,6 @@ config SYS_SOC
 	default "fsl-layerscape"
 
 config SYS_CONFIG_NAME
-	default "ls2085a_simu"
+	default "ls2080a_simu"
 
 endif
diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS
new file mode 100644
index 0000000000..03ca168f15
--- /dev/null
+++ b/board/freescale/ls2080a/MAINTAINERS
@@ -0,0 +1,10 @@
+LS2080A BOARD
+M:	York Sun <yorksun@freescale.com>
+S:	Maintained
+F:	board/freescale/ls2080a/
+F:	include/configs/ls2080a_emu.h
+F:	configs/ls2080a_emu_defconfig
+F:	include/configs/ls2080a_simu.h
+F:	configs/ls2080a_simu_defconfig
+F:	configs/ls2085a_emu_defconfig
+F:	configs/ls2085a_simu_defconfig
diff --git a/board/freescale/ls2080a/Makefile b/board/freescale/ls2080a/Makefile
new file mode 100644
index 0000000000..47c7c748ea
--- /dev/null
+++ b/board/freescale/ls2080a/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2014-15 Freescale Semiconductor
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += ls2080a.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2085a/README b/board/freescale/ls2080a/README
index bc1d0bb4a7..7e53f1f1e4 100644
--- a/board/freescale/ls2085a/README
+++ b/board/freescale/ls2080a/README
@@ -1,4 +1,4 @@
-Freescale ls2085a_emu
+Freescale ls2080a_emu
 
 This is a emulator target with limited peripherals.
 
diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2080a/ddr.c
index 4884fa24d0..47d73ef75a 100644
--- a/board/freescale/ls2085a/ddr.c
+++ b/board/freescale/ls2080a/ddr.c
@@ -71,7 +71,7 @@ found:
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
 		/* force DDR bus width to 32 bits */
 		popts->data_bus_width = 1;
@@ -79,6 +79,7 @@ found:
 		popts->burst_length = DDR_BL8;
 		popts->bstopre = 0;	/* enable auto precharge */
 	}
+#endif
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed
diff --git a/board/freescale/ls2085a/ddr.h b/board/freescale/ls2080a/ddr.h
index 9958a68e3e..9958a68e3e 100644
--- a/board/freescale/ls2085a/ddr.h
+++ b/board/freescale/ls2080a/ddr.h
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2080a/ls2080a.c
index 27481e2ba3..827fbf0835 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2080a/ls2080a.c
@@ -41,11 +41,13 @@ void detail_board_ddr_info(void)
 	puts("\nDDR    ");
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
+#endif
 }
 
 int dram_init(void)
diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig
index 8d6acbac93..2f997e9de1 100644
--- a/board/freescale/ls2085aqds/Kconfig
+++ b/board/freescale/ls2080aqds/Kconfig
@@ -1,8 +1,8 @@
 
-if TARGET_LS2085AQDS
+if TARGET_LS2080AQDS
 
 config SYS_BOARD
-	default "ls2085aqds"
+	default "ls2080aqds"
 
 config SYS_VENDOR
 	default "freescale"
@@ -11,6 +11,6 @@ config SYS_SOC
 	default "fsl-layerscape"
 
 config SYS_CONFIG_NAME
-	default "ls2085aqds"
+	default "ls2080aqds"
 
 endif
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
new file mode 100644
index 0000000000..6f99ad0d91
--- /dev/null
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -0,0 +1,10 @@
+LS2080A BOARD
+M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+S:	Maintained
+F:	board/freescale/ls2080aqds/
+F:	board/freescale/ls2080a/ls2080aqds.c
+F:	include/configs/ls2080aqds.h
+F:	configs/ls2080aqds_defconfig
+F:	configs/ls2080aqds_nand_defconfig
+F:	configs/ls2085aqds_defconfig
+F:	configs/ls2085aqds_nand_defconfig
diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2080aqds/Makefile
index da69a7d22d..e0da8a5d77 100644
--- a/board/freescale/ls2085aqds/Makefile
+++ b/board/freescale/ls2080aqds/Makefile
@@ -4,6 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += ls2085aqds.o
+obj-y += ls2080aqds.o
 obj-y += ddr.o
 obj-y += eth.o
diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2080aqds/README
index e4a6f69bfc..375e97c9b0 100644
--- a/board/freescale/ls2085aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -1,19 +1,19 @@
 Overview
 --------
-The LS2085A Development System (QDS) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
-Layerscape Architecture processor. The LS2085AQDS provides validation and
-SW development platform for the Freescale LS2085A processor series, with
+The LS2080A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
+Layerscape Architecture processor. The LS2080AQDS provides validation and
+SW development platform for the Freescale LS2080A processor series, with
 a complete debugging environment.
 
-LS2085A SoC Overview
+LS2080A SoC Overview
 ------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
 processor cores with high-performance data path acceleration logic and network
 and peripheral bus interfaces required for networking, telecom/datacom,
 wireless infrastructure, and mil/aerospace applications.
 
-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:
 
  - Eight 64-bit ARM Cortex-A57 CPUs
  - 1 MB platform cache with ECC
@@ -50,7 +50,7 @@ The LS2085A SoC includes the following function and features:
  - Service processor (SP) provides pre-boot initialization and secure-boot
   capabilities
 
- LS2085AQDS board Overview
+ LS2080AQDS board Overview
  -----------------------
  - SERDES Connections, 16 lanes supporting:
       - PCI Express - 3.0
@@ -172,7 +172,7 @@ Supported PHY addresses during SGMII:
 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 
-Mapping DPMACx to PHY during QSGMII
+Mapping DPMACx to PHY during SGMII
 DPMAC1 -> PHY1-P0
 DPMAC2 -> PHY2-P0
 DPMAC3 -> PHY3-P0
diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2080aqds/ddr.c
index 8d71ae1264..ae681de35e 100644
--- a/board/freescale/ls2085ardb/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 	int slot;
@@ -79,7 +81,7 @@ found:
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
 		/* force DDR bus width to 32 bits */
 		popts->data_bus_width = 1;
@@ -114,6 +116,7 @@ found:
 		pdimm[slot].dq_mapping[16] = 0;
 		pdimm[slot].dq_mapping[17] = 0;
 	}
+#endif
 	/* To work at higher than 1333MT/s */
 	popts->half_strength_driver_enable = 0;
 	/*
diff --git a/board/freescale/ls2085aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h
index b76ea61ba0..b76ea61ba0 100644
--- a/board/freescale/ls2085aqds/ddr.h
+++ b/board/freescale/ls2080aqds/ddr.h
diff --git a/board/freescale/ls2085aqds/eth.c b/board/freescale/ls2080aqds/eth.c
index b8a2bf49e6..0637ecf2a7 100644
--- a/board/freescale/ls2085aqds/eth.c
+++ b/board/freescale/ls2080aqds/eth.c
@@ -18,16 +18,16 @@
 
 #include "../common/qixis.h"
 
-#include "ls2085aqds_qixis.h"
+#include "ls2080aqds_qixis.h"
 
 
 #ifdef CONFIG_FSL_MC_ENET
- /* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
+ /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  *   Bank 1 -> Lanes A, B, C, D, E, F, G, H
  *   Bank 2 -> Lanes A,B, C, D, E, F, G, H
  */
 
- /* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
+ /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
   * means that the mapping must be determined dynamically, or that the lane
   * maps to something other than a board slot.
   */
@@ -74,16 +74,16 @@ static int sgmii_riser_phy_addr[] = {
 #define SFP_TX		0
 
 static const char * const mdio_names[] = {
-	"LS2085A_QDS_MDIO0",
-	"LS2085A_QDS_MDIO1",
-	"LS2085A_QDS_MDIO2",
-	"LS2085A_QDS_MDIO3",
-	"LS2085A_QDS_MDIO4",
-	"LS2085A_QDS_MDIO5",
+	"LS2080A_QDS_MDIO0",
+	"LS2080A_QDS_MDIO1",
+	"LS2080A_QDS_MDIO2",
+	"LS2080A_QDS_MDIO3",
+	"LS2080A_QDS_MDIO4",
+	"LS2080A_QDS_MDIO5",
 	DEFAULT_WRIOP_MDIO2_NAME,
 };
 
-struct ls2085a_qds_mdio {
+struct ls2080a_qds_mdio {
 	u8 muxval;
 	struct mii_dev *realbus;
 };
@@ -95,7 +95,7 @@ static void sgmii_configure_repeater(int serdes_port)
 	int i, j, ret;
 	int dpmac_id = 0, dpmac, mii_bus = 0;
 	unsigned short value;
-	char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"};
+	char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
 	uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
 
 	uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
@@ -222,7 +222,7 @@ static void qsgmii_configure_repeater(int dpmac)
 	uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
 	uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
 
-	const char *dev = "LS2085A_QDS_MDIO0";
+	const char *dev = "LS2080A_QDS_MDIO0";
 	int ret = 0;
 	unsigned short value;
 
@@ -318,7 +318,7 @@ error:
 	return;
 }
 
-static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
+static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
 {
 	return mdio_names[muxval];
 }
@@ -326,7 +326,7 @@ static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
 struct mii_dev *mii_dev_for_muxval(u8 muxval)
 {
 	struct mii_dev *bus;
-	const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
+	const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
 
 	if (!name) {
 		printf("No bus for muxval %x\n", muxval);
@@ -343,7 +343,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval)
 	return bus;
 }
 
-static void ls2085a_qds_enable_SFP_TX(u8 muxval)
+static void ls2080a_qds_enable_SFP_TX(u8 muxval)
 {
 	u8 brdcfg9;
 
@@ -353,7 +353,7 @@ static void ls2085a_qds_enable_SFP_TX(u8 muxval)
 	QIXIS_WRITE(brdcfg[9], brdcfg9);
 }
 
-static void ls2085a_qds_mux_mdio(u8 muxval)
+static void ls2080a_qds_mux_mdio(u8 muxval)
 {
 	u8 brdcfg4;
 
@@ -365,54 +365,54 @@ static void ls2085a_qds_mux_mdio(u8 muxval)
 	}
 }
 
-static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
+static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
 				 int devad, int regnum)
 {
-	struct ls2085a_qds_mdio *priv = bus->priv;
+	struct ls2080a_qds_mdio *priv = bus->priv;
 
-	ls2085a_qds_mux_mdio(priv->muxval);
+	ls2080a_qds_mux_mdio(priv->muxval);
 
 	return priv->realbus->read(priv->realbus, addr, devad, regnum);
 }
 
-static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 				  int regnum, u16 value)
 {
-	struct ls2085a_qds_mdio *priv = bus->priv;
+	struct ls2080a_qds_mdio *priv = bus->priv;
 
-	ls2085a_qds_mux_mdio(priv->muxval);
+	ls2080a_qds_mux_mdio(priv->muxval);
 
 	return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 }
 
-static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
+static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
 {
-	struct ls2085a_qds_mdio *priv = bus->priv;
+	struct ls2080a_qds_mdio *priv = bus->priv;
 
 	return priv->realbus->reset(priv->realbus);
 }
 
-static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval)
+static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
 {
-	struct ls2085a_qds_mdio *pmdio;
+	struct ls2080a_qds_mdio *pmdio;
 	struct mii_dev *bus = mdio_alloc();
 
 	if (!bus) {
-		printf("Failed to allocate ls2085a_qds MDIO bus\n");
+		printf("Failed to allocate ls2080a_qds MDIO bus\n");
 		return -1;
 	}
 
 	pmdio = malloc(sizeof(*pmdio));
 	if (!pmdio) {
-		printf("Failed to allocate ls2085a_qds private data\n");
+		printf("Failed to allocate ls2080a_qds private data\n");
 		free(bus);
 		return -1;
 	}
 
-	bus->read = ls2085a_qds_mdio_read;
-	bus->write = ls2085a_qds_mdio_write;
-	bus->reset = ls2085a_qds_mdio_reset;
-	sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval));
+	bus->read = ls2080a_qds_mdio_read;
+	bus->write = ls2080a_qds_mdio_write;
+	bus->reset = ls2080a_qds_mdio_reset;
+	sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
 
 	pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 
@@ -474,8 +474,8 @@ static void initialize_dpmac_to_slot(void)
 		       serdes1_prtcl);
 		break;
 	default:
-		printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
-		       serdes1_prtcl);
+		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+		       __func__, serdes1_prtcl);
 		break;
 	}
 
@@ -505,13 +505,13 @@ static void initialize_dpmac_to_slot(void)
 		}
 		break;
 	default:
-		printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
-		       serdes2_prtcl);
+		printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
+		       __func__ , serdes2_prtcl);
 		break;
 	}
 }
 
-void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
+void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
 {
 	int lane, slot;
 	struct mii_dev *bus;
@@ -580,8 +580,8 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
 		}
 	break;
 	default:
-		printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
-		       serdes1_prtcl);
+		printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
+		       __func__ , serdes1_prtcl);
 	break;
 	}
 
@@ -626,13 +626,13 @@ serdes2:
 	}
 	break;
 	default:
-		printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
-		       serdes2_prtcl);
+		printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
+		       __func__, serdes2_prtcl);
 	break;
 	}
 }
 
-void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
+void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
 {
 	int lane = 0, slot;
 	struct mii_dev *bus;
@@ -706,7 +706,7 @@ void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
 	qsgmii_configure_repeater(dpmac_id);
 }
 
-void ls2085a_handle_phy_interface_xsgmii(int i)
+void ls2080a_handle_phy_interface_xsgmii(int i)
 {
 	struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 	int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@@ -725,7 +725,7 @@ void ls2085a_handle_phy_interface_xsgmii(int i)
 		 * error.
 		 */
 		wriop_set_phy_address(i, i + 4);
-		ls2085a_qds_enable_SFP_TX(SFP_TX);
+		ls2080a_qds_enable_SFP_TX(SFP_TX);
 
 		break;
 	default:
@@ -778,25 +778,25 @@ int board_eth_init(bd_t *bis)
 	fm_memac_mdio_init(bis, memac_mdio1_info);
 
 	/* Register the muxing front-ends to the MDIO buses */
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
 
-	ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
+	ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
 
 	for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
 		switch (wriop_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_QSGMII:
-			ls2085a_handle_phy_interface_qsgmii(i);
+			ls2080a_handle_phy_interface_qsgmii(i);
 			break;
 		case PHY_INTERFACE_MODE_SGMII:
-			ls2085a_handle_phy_interface_sgmii(i);
+			ls2080a_handle_phy_interface_sgmii(i);
 			break;
 		case PHY_INTERFACE_MODE_XGMII:
-			ls2085a_handle_phy_interface_xsgmii(i);
+			ls2080a_handle_phy_interface_xsgmii(i);
 			break;
 		default:
 			break;
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index b02d6e86b4..1f990720a8 100644
--- a/board/freescale/ls2085aqds/ls2085aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -21,7 +21,7 @@
 #include <hwconfig.h>
 
 #include "../common/qixis.h"
-#include "ls2085aqds_qixis.h"
+#include "ls2080aqds_qixis.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a
@@ -226,11 +226,13 @@ void detail_board_ddr_info(void)
 	puts("\nDDR    ");
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
+#endif
 }
 
 int dram_init(void)
@@ -294,6 +296,7 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	int err;
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
@@ -309,7 +312,9 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
-	fsl_mc_ldpaa_exit(bd);
+	err = fsl_mc_ldpaa_exit(bd);
+	if (err)
+		return err;
 #endif
 
 	return 0;
diff --git a/board/freescale/ls2085aqds/ls2085aqds_qixis.h b/board/freescale/ls2080aqds/ls2080aqds_qixis.h
index e281e5ffe0..e281e5ffe0 100644
--- a/board/freescale/ls2085aqds/ls2085aqds_qixis.h
+++ b/board/freescale/ls2080aqds/ls2080aqds_qixis.h
diff --git a/board/freescale/ls2085ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index cb40db9b55..fe02575cf9 100644
--- a/board/freescale/ls2085ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -1,8 +1,8 @@
 
-if TARGET_LS2085ARDB
+if TARGET_LS2080ARDB
 
 config SYS_BOARD
-	default "ls2085ardb"
+	default "ls2080ardb"
 
 config SYS_VENDOR
 	default "freescale"
@@ -11,6 +11,6 @@ config SYS_SOC
 	default "fsl-layerscape"
 
 config SYS_CONFIG_NAME
-	default "ls2085ardb"
+	default "ls2080ardb"
 
 endif
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
new file mode 100644
index 0000000000..c9f3459f78
--- /dev/null
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -0,0 +1,10 @@
+LS2080A BOARD
+M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+S:	Maintained
+F:	board/freescale/ls2080ardb/
+F:	board/freescale/ls2080a/ls2080ardb.c
+F:	include/configs/ls2080ardb.h
+F:	configs/ls2080ardb_defconfig
+F:	configs/ls2080ardb_nand_defconfig
+F:	configs/ls2085ardb_defconfig
+F:	configs/ls2085ardb_nand_defconfig
diff --git a/board/freescale/ls2085ardb/Makefile b/board/freescale/ls2080ardb/Makefile
index de383ccc0f..6a52167be1 100644
--- a/board/freescale/ls2085ardb/Makefile
+++ b/board/freescale/ls2080ardb/Makefile
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y += ls2085ardb.o eth_ls2085rdb.o
+obj-y += ls2080ardb.o eth_ls2080rdb.o
 obj-y += ddr.o
diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2080ardb/README
index 2f18243a8b..7fc2569648 100644
--- a/board/freescale/ls2085ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -1,17 +1,17 @@
 Overview
 --------
-The LS2085A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
+The LS2080A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
 Layerscape Architecture processor.
 
-LS2085A SoC Overview
+LS2080A SoC Overview
 ------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
 processor cores with high-performance data path acceleration logic and network
 and peripheral bus interfaces required for networking, telecom/datacom,
 wireless infrastructure, and mil/aerospace applications.
 
-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:
 
  - Eight 64-bit ARM Cortex-A57 CPUs
  - 1 MB platform cache with ECC
@@ -48,7 +48,7 @@ The LS2085A SoC includes the following function and features:
  - Service processor (SP) provides pre-boot initialization and secure-boot
   capabilities
 
- LS2085ARDB board Overview
+ LS2080ARDB board Overview
  -----------------------
  - SERDES Connections, 16 lanes supporting:
       - PCI Express - 3.0
diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2080ardb/ddr.c
index 8d71ae1264..ae681de35e 100644
--- a/board/freescale/ls2085aqds/ddr.c
+++ b/board/freescale/ls2080ardb/ddr.c
@@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
 	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 	int slot;
@@ -79,7 +81,7 @@ found:
 		pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
 		pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
 		pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (ctrl_num == CONFIG_DP_DDR_CTRL) {
 		/* force DDR bus width to 32 bits */
 		popts->data_bus_width = 1;
@@ -114,6 +116,7 @@ found:
 		pdimm[slot].dq_mapping[16] = 0;
 		pdimm[slot].dq_mapping[17] = 0;
 	}
+#endif
 	/* To work at higher than 1333MT/s */
 	popts->half_strength_driver_enable = 0;
 	/*
diff --git a/board/freescale/ls2085ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index bda9d4a40f..bda9d4a40f 100644
--- a/board/freescale/ls2085ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
diff --git a/board/freescale/ls2085ardb/eth_ls2085rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c
index d578757dfd..db50e4efa9 100644
--- a/board/freescale/ls2085ardb/eth_ls2085rdb.c
+++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c
@@ -97,7 +97,7 @@ int board_eth_init(bd_t *bis)
 
 		break;
 	default:
-		printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
+		printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
 		       srds_s1);
 		break;
 	}
diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 18953b8ecb..2ae9d6cf45 100644
--- a/board/freescale/ls2085ardb/ls2085ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -20,7 +20,7 @@
 #include <asm/arch/soc.h>
 
 #include "../common/qixis.h"
-#include "ls2085ardb_qixis.h"
+#include "ls2080ardb_qixis.h"
 
 #define PIN_MUX_SEL_SDHC	0x00
 #define PIN_MUX_SEL_DSPI	0x0a
@@ -192,11 +192,13 @@ void detail_board_ddr_info(void)
 	puts("\nDDR    ");
 	print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
 	print_ddr_info(0);
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (gd->bd->bi_dram[2].size) {
 		puts("\nDP-DDR ");
 		print_size(gd->bd->bi_dram[2].size, "");
 		print_ddr_info(CONFIG_DP_DDR_CTRL);
 	}
+#endif
 }
 
 int dram_init(void)
@@ -260,6 +262,7 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+	int err;
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
@@ -275,7 +278,9 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 #ifdef CONFIG_FSL_MC_ENET
 	fdt_fixup_board_enet(blob);
-	fsl_mc_ldpaa_exit(bd);
+	err = fsl_mc_ldpaa_exit(bd);
+	if (err)
+		return err;
 #endif
 
 	return 0;
diff --git a/board/freescale/ls2085ardb/ls2085ardb_qixis.h b/board/freescale/ls2080ardb/ls2080ardb_qixis.h
index cb60c00c6c..cb60c00c6c 100644
--- a/board/freescale/ls2085ardb/ls2085ardb_qixis.h
+++ b/board/freescale/ls2080ardb/ls2080ardb_qixis.h
diff --git a/board/freescale/ls2085a/MAINTAINERS b/board/freescale/ls2085a/MAINTAINERS
deleted file mode 100644
index 90b4e4715d..0000000000
--- a/board/freescale/ls2085a/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-LS2085A BOARD
-M:	York Sun <yorksun@freescale.com>
-S:	Maintained
-F:	board/freescale/ls2085a/
-F:	include/configs/ls2085a_emu.h
-F:	configs/ls2085a_emu_defconfig
-F:	include/configs/ls2085a_simu.h
-F:	configs/ls2085a_simu_defconfig
diff --git a/board/freescale/ls2085a/Makefile b/board/freescale/ls2085a/Makefile
deleted file mode 100644
index 701b35cd59..0000000000
--- a/board/freescale/ls2085a/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright 2014 Freescale Semiconductor
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y += ls2085a.o
-obj-y += ddr.o
diff --git a/board/freescale/ls2085aqds/MAINTAINERS b/board/freescale/ls2085aqds/MAINTAINERS
deleted file mode 100644
index fbed672601..0000000000
--- a/board/freescale/ls2085aqds/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-LS2085A BOARD
-M:	Prabhakar Kushwaha <prabhakar@freescale.com>
-S:	Maintained
-F:	board/freescale/ls2085aqds/
-F:	board/freescale/ls2085a/ls2085aqds.c
-F:	include/configs/ls2085aqds.h
-F:	configs/ls2085aqds_defconfig
-F:	configs/ls2085aqds_nand_defconfig
diff --git a/board/freescale/ls2085ardb/MAINTAINERS b/board/freescale/ls2085ardb/MAINTAINERS
deleted file mode 100644
index d5cce40b21..0000000000
--- a/board/freescale/ls2085ardb/MAINTAINERS
+++ /dev/null
@@ -1,8 +0,0 @@
-LS2085A BOARD
-M:	Prabhakar Kushwaha <prabhakar@freescale.com>
-S:	Maintained
-F:	board/freescale/ls2085ardb/
-F:	board/freescale/ls2085a/ls2085ardb.c
-F:	include/configs/ls2085ardb.h
-F:	configs/ls2085ardb_defconfig
-F:	configs/ls2085ardb_nand_defconfig