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authorValentin Longchamp <valentin.longchamp@keymile.com>2013-10-18 11:47:24 +0200
committerYork Sun <yorksun@freescale.com>2013-10-24 09:36:26 -0700
commit877bfe37dc00b0ae59f37742954a62bce3fdf3a0 (patch)
treef0ea1e47a471cd0e255f55090d63c7286347dc8f /board/keymile/kmp204x/eth.c
parent935b402eaec0f78ffdafd614aa8176a777d8b6d9 (diff)
downloadtalos-obmc-uboot-877bfe37dc00b0ae59f37742954a62bce3fdf3a0.tar.gz
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mpc85xx: introduce the kmp204x reference design support
This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). There is currently only one prototype board that is based on this design and this patch also introduces it. The board is called kmlion1. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> kmp204x: update the ENV #define The comments had to be refined as well as the total size Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix ddr.c] Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/keymile/kmp204x/eth.c')
-rw-r--r--board/keymile/kmp204x/eth.c71
1 files changed, 71 insertions, 0 deletions
diff --git a/board/keymile/kmp204x/eth.c b/board/keymile/kmp204x/eth.c
new file mode 100644
index 0000000000..a0731055a2
--- /dev/null
+++ b/board/keymile/kmp204x/eth.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2013 Keymile AG
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <phy.h>
+
+int board_eth_init(bd_t *bis)
+{
+ int ret = 0;
+#ifdef CONFIG_FMAN_ENET
+ struct fsl_pq_mdio_info dtsec_mdio_info;
+
+ printf("Initializing Fman\n");
+
+ dtsec_mdio_info.regs =
+ (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the real 1G MDIO bus */
+ fsl_pq_mdio_init(bis, &dtsec_mdio_info);
+
+ /* DTESC1/2 don't have a PHY, they are temporarily disabled
+ * so that u-boot doesn't try to unsuccessfuly enable them */
+ fm_disable_port(FM1_DTSEC1);
+ fm_disable_port(FM1_DTSEC2);
+
+ /*
+ * Program RGMII DTSEC5 (FM1 MAC5) on the EC2 physical itf
+ * This is the debug interface, the only one used in u-boot
+ */
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ fm_info_set_mdio(FM1_DTSEC5,
+ miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+
+ ret = cpu_eth_init(bis);
+
+ /* reenable DTSEC1/2 for later (kernel) */
+ fm_enable_port(FM1_DTSEC1);
+ fm_enable_port(FM1_DTSEC2);
+#endif
+
+ return ret;
+}
+
+#if defined(CONFIG_PHYLIB) && defined(CONFIG_PHY_MARVELL)
+
+#define mv88E1118_PAGE_REG 22
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (phydev->addr == CONFIG_SYS_FM1_DTSEC5_PHY_ADDR) {
+ /* driver config is good */
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ /* but we still need to fix the LEDs */
+ phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0003);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x0840);
+ phy_write(phydev, MDIO_DEVAD_NONE, mv88E1118_PAGE_REG, 0x0000);
+ }
+
+ return 0;
+}
+#endif
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