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| author | Shengzhou Liu <Shengzhou.Liu@nxp.com> | 2016-05-04 10:20:22 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-06-03 14:06:57 -0700 |
| commit | e04f9d0c2f5dec275eb550317c6bad2d8bbfb209 (patch) | |
| tree | fe6ee40fd32a3abfe8f52b3cf797f5bc3172248b /board/freescale/t104xrdb | |
| parent | d8e5163ad81a2810c66a9a98e5111769378f5f5f (diff) | |
| download | talos-obmc-uboot-e04f9d0c2f5dec275eb550317c6bad2d8bbfb209.tar.gz talos-obmc-uboot-e04f9d0c2f5dec275eb550317c6bad2d8bbfb209.zip | |
board/freescale: Update ddr clk_adjust
This patch updates clk_adjust to actual value for boards with
T-series and LS-series SoCs to match the setting of clk_adjust
in latest ddr driver.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'board/freescale/t104xrdb')
| -rw-r--r-- | board/freescale/t104xrdb/ddr.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index b9c02f7fe0..012991cf46 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a}, + {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a}, #elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, - {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, - {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, - {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, - {1, 833, 4, 4, 6, 0x06060607, 0x08080807}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807}, - {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, - {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 833, 4, 8, 6, 0x06060607, 0x08080807}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807}, + {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 833, 4, 8, 6, 0x06060607, 0x08080807}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807}, + {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, #else #error DDR type not defined #endif |
