diff options
| author | York Sun <yorksun@freescale.com> | 2012-02-29 12:36:51 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-04-24 23:58:30 -0500 |
| commit | 1ba62f10172ead798a8176435cfffff2f79f21c5 (patch) | |
| tree | 5e9b575825060fae4ebefa3193ad5f1124c0fefd /board/freescale/p1_p2_rdb_pc | |
| parent | 119a55f9cff4884a0ad3353d8752ee8787e232da (diff) | |
| download | talos-obmc-uboot-1ba62f10172ead798a8176435cfffff2f79f21c5.tar.gz talos-obmc-uboot-1ba62f10172ead798a8176435cfffff2f79f21c5.zip | |
powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/p1_p2_rdb_pc')
| -rw-r--r-- | board/freescale/p1_p2_rdb_pc/ddr.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index f0cbde72ab..88ba56f457 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -15,7 +15,7 @@ #include <asm/io.h> #include <asm/fsl_law.h> -#ifdef CONFIG_DDR_RAW_TIMING +#ifdef CONFIG_SYS_DDR_RAW_TIMING #if defined(CONFIG_P1020RDB_PROTO) || \ defined(CONFIG_P1021RDB) || \ defined(CONFIG_P1020UTM) @@ -204,7 +204,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, return 0; } -#endif /* CONFIG_DDR_RAW_TIMING */ +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ /* Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) |
