diff options
| author | chenhui zhao <chenhui.zhao@freescale.com> | 2015-05-15 14:42:30 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-08-03 12:06:36 -0700 |
| commit | 933db81c0494f692bbd384db11f7bab43706c87c (patch) | |
| tree | 85f174b25cf1a9a52ed7d45632849b4946b8b3ae /board/freescale/ls1021atwr/ls1021atwr.c | |
| parent | 99e1bd4241262440dce8950ccadb9d8588b0479b (diff) | |
| download | talos-obmc-uboot-933db81c0494f692bbd384db11f7bab43706c87c.tar.gz talos-obmc-uboot-933db81c0494f692bbd384db11f7bab43706c87c.zip | |
armv7/ls1021atwr: program the regulator for deep sleep
Program the external regulator to switch off voltage in deep sleep.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls1021atwr/ls1021atwr.c')
| -rw-r--r-- | board/freescale/ls1021atwr/ls1021atwr.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index d62323e3ed..698f755033 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -582,6 +582,37 @@ struct smmu_stream_id dev_stream_id[] = { { 0x18c, 0x0e, "DEBUG" }, }; +#ifdef CONFIG_DEEP_SLEEP +/* program the regulator (MC34VR500) to support deep sleep */ +void ls1twr_program_regulator(void) +{ + unsigned int i2c_bus; + u8 i2c_device_id; + +#define LS1TWR_I2C_BUS_MC34VR500 1 +#define MC34VR500_ADDR 0x8 +#define MC34VR500_DEVICEID 0x4 +#define MC34VR500_DEVICEID_MASK 0x0f + + i2c_bus = i2c_get_bus_num(); + i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500); + i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) & + MC34VR500_DEVICEID_MASK; + if (i2c_device_id != MC34VR500_DEVICEID) { + printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n"); + return; + } + + i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4); + i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4); + i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38); + i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37); + i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30); + + i2c_set_bus_num(i2c_bus); +} +#endif + int board_init(void) { #ifndef CONFIG_SYS_FSL_NO_SERDES @@ -604,6 +635,9 @@ int board_init(void) u_qe_init(); #endif +#ifdef CONFIG_DEEP_SLEEP + ls1twr_program_regulator(); +#endif return 0; } |
