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| author | Stefan Roese <sr@denx.de> | 2007-03-06 07:47:04 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-06 07:47:04 +0100 |
| commit | 07b7b0037aac5102939917d7cbe561b5c0d5aa44 (patch) | |
| tree | f9dee6436517274555fea9d0bc551f221a9d0640 /board/amcc/sequoia/sdram.c | |
| parent | fdd1d6dcc97c595bd9d598ed3b22a7038781272c (diff) | |
| download | talos-obmc-uboot-07b7b0037aac5102939917d7cbe561b5c0d5aa44.tar.gz talos-obmc-uboot-07b7b0037aac5102939917d7cbe561b5c0d5aa44.zip | |
[PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.
For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/sequoia/sdram.c')
| -rw-r--r-- | board/amcc/sequoia/sdram.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index 77f1438448..f8b837ed28 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -6,7 +6,7 @@ * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com * - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -379,16 +379,18 @@ void denali_core_search_data_eye(unsigned long memory_size) long int initdram (int board_type) { #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + ulong speed = get_bus_freq(0); + mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02030602); - mtsdram(DDR0_04, 0x13030300); - mtsdram(DDR0_05, 0x0202050E); - mtsdram(DDR0_06, 0x0104C823); + mtsdram(DDR0_04, 0x0A020200); + mtsdram(DDR0_05, 0x02020308); + mtsdram(DDR0_06, 0x0102C812); mtsdram(DDR0_07, 0x000D0100); - mtsdram(DDR0_08, 0x02360001); + mtsdram(DDR0_08, 0x02430001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000300); mtsdram(DDR0_11, 0x0027C800); @@ -402,13 +404,16 @@ long int initdram (int board_type) mtsdram(DDR0_22, 0x00267F0B); mtsdram(DDR0_23, 0x00000000); mtsdram(DDR0_24, 0x01010002); - mtsdram(DDR0_26, 0x5B260181); + if (speed > 133333333) + mtsdram(DDR0_26, 0x5B26050C); + else + mtsdram(DDR0_26, 0x5B260408); mtsdram(DDR0_27, 0x0000682B); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000006); - mtsdram(DDR0_43, 0x050A0200); - mtsdram(DDR0_44, 0x00000005); + mtsdram(DDR0_43, 0x030A0200); + mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); wait_for_dlllock(); |
