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authorMartha Marx <mmarx@silicontkx.com>2008-05-29 14:23:25 -0400
committerJohn Rigby <jrigby@freescale.com>2008-07-10 11:36:42 -0600
commitf31c49db2a5e076f415c0785eb37f67f2faa5fc8 (patch)
tree5d89a520255ea95f33adbffc50660a209033eaf3 /board/ads5121
parent16bee7b0dc294ee01ca2434aa1dd3bd717a69615 (diff)
downloadtalos-obmc-uboot-f31c49db2a5e076f415c0785eb37f67f2faa5fc8.tar.gz
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Configuration changes for ADS5121 Rev 3
ADS5121 Rev 3 board is now the default config config targets are now ads5121_config Rev 3 board with PCI M41T62 on board RTC 512MB DRAM ads5121_rev2_config Rev 2 board with No PCI 256MB DRAM Signed-off-by: Martha Marx <mmarx@silicontkx.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: John Rigby <jrigby@freescale.com>
Diffstat (limited to 'board/ads5121')
-rw-r--r--board/ads5121/README9
-rw-r--r--board/ads5121/ads5121.c19
2 files changed, 26 insertions, 2 deletions
diff --git a/board/ads5121/README b/board/ads5121/README
new file mode 100644
index 0000000000..f2d1df3c9f
--- /dev/null
+++ b/board/ads5121/README
@@ -0,0 +1,9 @@
+To configure for the current (Rev 3.x) ADS5121
+ make ads5121_config
+This will automatically include PCI, the Real Time CLock, add backup flash
+ability and set the correct frequency and memory configuration.
+
+To configure for the older Rev 2 ADS5121 type (this will not have PCI)
+ make ads5121_rev2_config
+
+
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index 130b81d8dc..de59991d2a 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -26,7 +26,9 @@
#include <asm/bitops.h>
#include <command.h>
#include <fdt_support.h>
-
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
/* Clocks in use */
#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
CLOCK_SCCR1_LPC_EN | \
@@ -75,8 +77,21 @@ int board_early_init_f (void)
* Without this the flash identification routine fails, as it needs to issue
* write commands in order to establish the device ID.
*/
- *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+#ifdef CONFIG_ADS5121_REV2
+ *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+#else
+ if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
+ *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+ } else {
+ /* running from Backup flash */
+ *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
+ }
+#endif
+ /*
+ * Configure Flash Speed
+ */
+ *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
/*
* Enable clocks
*/
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