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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2015-02-27 02:26:52 +0900
committerMasahiro Yamada <yamada.m@jp.panasonic.com>2015-03-01 00:02:40 +0900
commitd3384bf77eb9a202d8218e1fe1da2f21af034aa7 (patch)
tree9cad48dc39695069846b887d77a86dc12486866f /arch
parent198a97a6abe7090109002baea0d2cb46070955aa (diff)
downloadtalos-obmc-uboot-d3384bf77eb9a202d8218e1fe1da2f21af034aa7.tar.gz
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ARM: UniPhier: reset NAND core in SPL for non-NAND boot mode
For all the UniPhier SoCs so far, the reset signal of the NAND core is automatically deasserted after the PLL gets stabled. (The bit 2 of SC_RSTCTRL is default to one.) This causes a fatal problem on the NAND controller of PH1-LD4. For that SoC, the NAND I/O pins are not set up yet at the power-on reset except the NAND boot mode. As a result, the NAND controller begins automatic device scanning with wrong I/O pins and finally hangs up. Actually, U-Boot dies after printing "NAND:" on the console unless the boot mode latch detected the NAND boot mode. To work around this problem, reset the NAND core in SPL for non-NAND boot modes. If CONFIG_NAND_DENALI is enabled, the reset signal is deasserted again in U-Boot proper. At this time, I/O pins have been correctly set up, the device scanning should succeed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c
index ae4185fa90..37bb79e25a 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c
+++ b/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c
@@ -5,6 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <common.h>
+#include <spl.h>
#include <asm/io.h>
#include <mach/sc-regs.h>
@@ -14,7 +16,10 @@ void early_clkrst_init(void)
/* deassert reset */
tmp = readl(SC_RSTCTRL);
+
tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
+ if (spl_boot_device() != BOOT_DEVICE_NAND)
+ tmp &= ~SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
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