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authorMarek Vasut <marex@denx.de>2014-09-08 14:08:45 +0200
committerMarek Vasut <marex@denx.de>2014-10-06 17:46:50 +0200
commitabb25f4e9529c1b91d651c74af9bd3f1c955437b (patch)
tree04228a250bddd8859685c473fe6fdcee05ee5252 /arch
parent230fe9b202ff0ca396ad9a564816cc87d42daa6e (diff)
downloadtalos-obmc-uboot-abb25f4e9529c1b91d651c74af9bd3f1c955437b.tar.gz
talos-obmc-uboot-abb25f4e9529c1b91d651c74af9bd3f1c955437b.zip
arm: socfpga: reset: Add function to reset FPGA bridges
Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/socfpga/reset_manager.c38
-rw-r--r--arch/arm/include/asm/arch-socfpga/reset_manager.h2
2 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index badc569582..1d3a95d0c8 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
+#include <asm/arch/fpga_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -50,6 +51,43 @@ void reset_deassert_peripherals_handoff(void)
writel(0, &reset_manager_base->per_mod_reset);
}
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+void socfpga_bridges_reset(int enable)
+{
+ /* For SoCFPGA-VT, this is NOP. */
+}
+#else
+
+#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
+#define L3REGS_REMAP_OCRAM_MASK 0x01
+
+void socfpga_bridges_reset(int enable)
+{
+ const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+ L3REGS_REMAP_HPS2FPGA_MASK |
+ L3REGS_REMAP_OCRAM_MASK;
+
+ if (enable) {
+ /* brdmodrst */
+ writel(0xffffffff, &reset_manager_base->brg_mod_reset);
+ } else {
+ /* Check signal from FPGA. */
+ if (fpgamgr_poll_fpga_ready()) {
+ /* FPGA not ready. Wait for watchdog timeout. */
+ printf("%s: fpga not ready, hanging.\n", __func__);
+ hang();
+ }
+
+ /* brdmodrst */
+ writel(0, &reset_manager_base->brg_mod_reset);
+
+ /* Remap the bridges into memory map */
+ writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+ }
+}
+#endif
+
/* Change the reset state for EMAC 0 and EMAC 1 */
void socfpga_emac_reset(int enable)
{
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 3c5ab401e1..1857b80b3e 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,8 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_reset(int enable);
+
void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void);
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