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authorMichal Simek <michal.simek@xilinx.com>2015-04-20 12:56:24 +0200
committerMichal Simek <michal.simek@xilinx.com>2015-05-25 10:52:03 +0200
commita2ec7fb906ef43e478c4b860cad80b0f1e13905b (patch)
treee4a872e1507f4be4698997f17770eb6a3de03ea9 /arch
parenta84988c76d1dbca2dbe870d6b4f0ad398f287f85 (diff)
downloadtalos-obmc-uboot-a2ec7fb906ef43e478c4b860cad80b0f1e13905b.tar.gz
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zynq: Use system timer implementation instead of our
Don't use error-prone arch timer code and instead use system timer implementation to simplify our code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-zynq/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-zynq/timer.c83
2 files changed, 1 insertions, 83 deletions
diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
index e2e0b7321a..9a51d6ba3b 100644
--- a/arch/arm/mach-zynq/include/mach/hardware.h
+++ b/arch/arm/mach-zynq/include/mach/hardware.h
@@ -12,7 +12,6 @@
#define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
#define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
#define ZYNQ_SCU_BASEADDR 0xF8F00000
-#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
#define ZYNQ_GEM_BASEADDR0 0xE000B000
#define ZYNQ_GEM_BASEADDR1 0xE000C000
#define ZYNQ_SDHCI_BASEADDR0 0xE0100000
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 5ed9642df9..8ff82dc930 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -78,91 +78,10 @@ int timer_init(void)
}
/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-ulong get_timer_masked(void)
-{
- ulong now;
-
- now = readl(&timer_base->counter) /
- (gd->arch.timer_rate_hz / CONFIG_SYS_HZ);
-
- if (gd->arch.lastinc >= now) {
- /* Normal mode */
- gd->arch.tbl += gd->arch.lastinc - now;
- } else {
- /* We have an overflow ... */
- gd->arch.tbl += gd->arch.lastinc + (TIMER_LOAD_VAL /
- (gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) -
- now + 1;
- }
- gd->arch.lastinc = now;
-
- return gd->arch.tbl;
-}
-
-void __udelay(unsigned long usec)
-{
- u32 countticks;
- u32 timeend;
- u32 timediff;
- u32 timenow;
-
- if (usec == 0)
- return;
-
- countticks = lldiv(((unsigned long long)gd->arch.timer_rate_hz * usec),
- 1000000);
-
- /* decrementing timer */
- timeend = readl(&timer_base->counter) - countticks;
-
-#if TIMER_LOAD_VAL != 0xFFFFFFFF
- /* do not manage multiple overflow */
- if (countticks >= TIMER_LOAD_VAL)
- countticks = TIMER_LOAD_VAL - 1;
-#endif
-
- do {
- timenow = readl(&timer_base->counter);
-
- if (timenow >= timeend) {
- /* normal case */
- timediff = timenow - timeend;
- } else {
- if ((TIMER_LOAD_VAL - timeend + timenow) <=
- countticks) {
- /* overflow */
- timediff = TIMER_LOAD_VAL - timeend + timenow;
- } else {
- /* missed the exact match */
- break;
- }
- }
- } while (timediff > 0);
-}
-
-/* Timer without interrupts */
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
- return CONFIG_SYS_HZ;
+ return gd->arch.timer_rate_hz;
}
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