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author | Stefan Roese <sr@denx.de> | 2015-04-24 10:49:11 +0200 |
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committer | Luka Perkov <luka.perkov@sartura.hr> | 2015-07-23 10:37:36 +0200 |
commit | 9f62b44ec7afabd2eea7d3bde14b6542739be249 (patch) | |
tree | 7417358a090a511edc740c233d9bfa534422822d /arch | |
parent | e3cccf9eb2ed6e25d603272719bf0cad5561826c (diff) | |
download | talos-obmc-uboot-9f62b44ec7afabd2eea7d3bde14b6542739be249.tar.gz talos-obmc-uboot-9f62b44ec7afabd2eea7d3bde14b6542739be249.zip |
arm: mvebu: Disable MMU before changing register base address
Only with disabled MMU its possible to switch the base register address on
Armada 38x. Without this the SDRAM located at >= 0x4000.0000 is also not
accessible, as its still locked to cache.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-mvebu/cpu.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 9bc9f002d8..9496d5fc5b 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -163,6 +163,14 @@ static void update_sdram_window_sizes(void) } } +void mmu_disable(void) +{ + asm volatile( + "mrc p15, 0, r0, c1, c0, 0\n" + "bic r0, #1\n" + "mcr p15, 0, r0, c1, c0, 0\n"); +} + #ifdef CONFIG_ARCH_CPU_INIT static void set_cbar(u32 addr) { @@ -172,6 +180,16 @@ static void set_cbar(u32 addr) int arch_cpu_init(void) { +#ifndef CONFIG_SPL_BUILD + /* + * Only with disabled MMU its possible to switch the base + * register address on Armada 38x. Without this the SDRAM + * located at >= 0x4000.0000 is also not accessible, as its + * still locked to cache. + */ + mmu_disable(); +#endif + /* Linux expects the internal registers to be at 0xf1000000 */ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG); set_cbar(SOC_REGS_PHY_BASE + 0xC000); |