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authorMasahiro Yamada <yamada.masahiro@socionext.com>2015-09-22 00:27:34 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2015-09-25 00:27:53 +0900
commit8497ccc4c23beae38130489d85c97ae38058f20b (patch)
tree9becb4f338637b145b31606c4e157e320a788987 /arch
parentc8df23cf33571eda2cc22277a8f448e6221f8409 (diff)
downloadtalos-obmc-uboot-8497ccc4c23beae38130489d85c97ae38058f20b.tar.gz
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ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*
I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-uniphier/Kconfig14
-rw-r--r--arch/arm/mach-uniphier/Makefile8
-rw-r--r--arch/arm/mach-uniphier/include/mach/ddrphy-regs.h3
-rw-r--r--arch/arm/mach-uniphier/include/mach/sc-regs.h2
-rw-r--r--arch/arm/mach-uniphier/ph1-pro4/pll_init.c2
5 files changed, 14 insertions, 15 deletions
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 28d574fbb8..d7a19c6772 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -8,20 +8,20 @@ config UNIPHIER_SMP
choice
prompt "UniPhier SoC select"
- default MACH_PH1_PRO4
+ default ARCH_UNIPHIER_PH1_PRO4
-config MACH_PH1_SLD3
+config ARCH_UNIPHIER_PH1_SLD3
bool "PH1-sLD3"
select UNIPHIER_SMP
-config MACH_PH1_LD4
+config ARCH_UNIPHIER_PH1_LD4
bool "PH1-LD4"
-config MACH_PH1_PRO4
+config ARCH_UNIPHIER_PH1_PRO4
bool "PH1-Pro4"
select UNIPHIER_SMP
-config MACH_PH1_SLD8
+config ARCH_UNIPHIER_PH1_SLD8
bool "PH1-sLD8"
endchoice
@@ -53,11 +53,11 @@ choice
config DDR_FREQ_1600
bool "DDR3 1600"
- depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4
+ depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4
config DDR_FREQ_1333
bool "DDR3 1333"
- depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8
+ depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_SLD8
endchoice
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index df6a569b9a..d30cc27009 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -31,7 +31,7 @@ obj-y += timer.o
obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
-obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/
-obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
-obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
-obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += ph1-sld3/
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ph1-ld4/
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ph1-pro4/
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ph1-sld8/
diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
index fce0c01246..01f5c52c9c 100644
--- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
@@ -156,7 +156,8 @@ struct ddrphy {
/* SoC-specific parameters */
#define NR_DATX8_PER_DDRPHY 2
-#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define NR_DDRPHY_PER_CH 1
#else
#define NR_DDRPHY_PER_CH 2
diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h
index df50294077..9d697b16ee 100644
--- a/arch/arm/mach-uniphier/include/mach/sc-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h
@@ -9,7 +9,7 @@
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
-#if defined(CONFIG_MACH_PH1_SLD3)
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
#define SC_BASE_ADDR 0xf1840000
#else
#define SC_BASE_ADDR 0x61840000
diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c
index d693368816..8ae8ed65b8 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c
+++ b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c
@@ -54,12 +54,10 @@ static void vpll_init(void)
tmp = readl(SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-#if defined(CONFIG_MACH_PH1_PRO4)
/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
return;
-#endif
/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
tmp = readl(SC_VPLL27ACTRL);
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