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authorSricharan R <r.sricharan@ti.com>2013-05-30 03:19:35 +0000
committerTom Rini <trini@ti.com>2013-06-10 08:43:10 -0400
commit81ede187c3e4233c08ab30900e86f5e0ec2c4624 (patch)
tree4eff76ffa1424225a86cc68df9cbdb77c50be528 /arch
parentf9b814a8e99390d19628bc1b67c9567fc485d918 (diff)
downloadtalos-obmc-uboot-81ede187c3e4233c08ab30900e86f5e0ec2c4624.tar.gz
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ARM: DRA7xx: Correct SRAM END address
NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h11
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 43a629f353..06171d017b 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -169,13 +169,14 @@ struct s32ktimer {
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
-/*
- * Non-secure SRAM Addresses
- * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
- * at 0x40304000(EMU base) so that our code works for both EMU and GP
- */
+#ifdef CONFIG_DRA7XX
+#define NON_SECURE_SRAM_START 0x40300000
+#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
+#else
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
+#endif
+
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000
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