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authorTom Rini <trini@konsulko.com>2016-05-24 11:59:02 -0400
committerTom Rini <trini@konsulko.com>2016-05-24 11:59:02 -0400
commit2ee490a0245b65826a8ce8e42e34c9bf805d3656 (patch)
treec53f7d3513bd284b181d3aaa61534a0d62751884 /arch
parentec8fb48ce98987065493b27422200897cf0909f8 (diff)
parent0a71cd77290ca317ecf6f15984a91abbee741e09 (diff)
downloadtalos-obmc-uboot-2ee490a0245b65826a8ce8e42e34c9bf805d3656.tar.gz
talos-obmc-uboot-2ee490a0245b65826a8ce8e42e34c9bf805d3656.zip
Merge branch 'master' of git://git.denx.de/u-boot-net
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/dts/am4372.dtsi1
-rw-r--r--arch/arm/dts/dra7.dtsi3
-rw-r--r--arch/arm/include/asm/arch-omap5/cpu.h12
3 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index c95d1d3b35..3ffa8e016e 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -547,6 +547,7 @@
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
+ syscon = <&scm_conf>;
ranges;
davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index e7fecf7656..0f242e6489 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1411,7 +1411,7 @@
ti,irqs-safe-map = <0>;
};
- mac: ethernet@4a100000 {
+ mac: ethernet@48484000 {
compatible = "ti,cpsw";
ti,hwmods = "gmac";
clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
@@ -1426,6 +1426,7 @@
active_slave = <0>;
cpts_clock_mult = <0x80000000>;
cpts_clock_shift = <29>;
+ syscon = <&scm_conf>;
reg = <0x48484000 0x1000
0x48485200 0x2E00>;
#address-cells = <1>;
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index b1513e9aaf..683d905333 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -116,4 +116,16 @@ struct watchdog {
#define CPSW_BASE 0x48484000
#define CPSW_MDIO_BASE 0x48485000
+/* gmii_sel register defines */
+#define GMII1_SEL_MII 0x0
+#define GMII1_SEL_RMII 0x1
+#define GMII1_SEL_RGMII 0x2
+#define GMII2_SEL_MII (GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII (GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
#endif /* _CPU_H */
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