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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-05-24 21:13:57 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2016-05-26 00:35:26 +0900
commit0bd20207ab2d874842161cab37c213310d785b24 (patch)
treeda95cd1c624176e51bd12a9b709e968afd89205f /arch
parentfc15b9beed05dec6cc092c265042381a0eadb0e9 (diff)
downloadtalos-obmc-uboot-0bd20207ab2d874842161cab37c213310d785b24.tar.gz
talos-obmc-uboot-0bd20207ab2d874842161cab37c213310d785b24.zip
ARM: uniphier: disable cache in SPL of PH1-LD20
The Boot ROM has enabled D-cache and MMU setting DDR memory area as Normal Memory in its page table. Disable D-cache and MMU before jumping to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-uniphier/init/init-ld20.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c
index 660ad457dc..7f66053e1f 100644
--- a/arch/arm/mach-uniphier/init/init-ld20.c
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -51,5 +51,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
led_puts("L5");
+ dcache_disable();
+
return 0;
}
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