diff options
| author | York Sun <yorksun@freescale.com> | 2015-03-23 10:41:35 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-04-23 16:46:51 -0700 |
| commit | ab10d73d2fc13bd5baf5024e54ad92641d238bdb (patch) | |
| tree | 4cdd86c34c58130f328009d4b52a325db9857f93 /arch | |
| parent | 8b06460e5518eeec449298c91fb1424b36c9b305 (diff) | |
| download | talos-obmc-uboot-ab10d73d2fc13bd5baf5024e54ad92641d238bdb.tar.gz talos-obmc-uboot-ab10d73d2fc13bd5baf5024e54ad92641d238bdb.zip | |
armv8/fsl-lsch3: Implement workaround for I2C erratum A009203
This erratum requires setting GLITCH_EN bit in debug register to
enable digital filter to improve clock stability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/soc.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c index ca00108e40..2538001bca 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c @@ -37,11 +37,45 @@ static void erratum_rcw_src(void) #endif } +#define I2C_DEBUG_REG 0x6 +#define I2C_GLITCH_EN 0x8 +/* + * This erratum requires setting glitch_en bit to enable + * digital glitch filter to improve clock stability. + */ +static void erratum_a009203(void) +{ + u8 __iomem *ptr; +#ifdef CONFIG_SYS_I2C +#ifdef I2C1_BASE_ADDR + ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#ifdef I2C2_BASE_ADDR + ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#ifdef I2C3_BASE_ADDR + ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#ifdef I2C4_BASE_ADDR + ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG); + + writeb(I2C_GLITCH_EN, ptr); +#endif +#endif +} + void fsl_lsch3_early_init_f(void) { erratum_a008751(); erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ + erratum_a009203(); } #ifdef CONFIG_SPL_BUILD |
