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authorGabriel Huau <contact@huau-gabriel.fr>2015-04-25 13:16:57 -0700
committerSimon Glass <sjg@chromium.org>2015-04-29 18:51:49 -0600
commit8827227889848433d464f31c76c8be9d13567623 (patch)
tree0d13ebeefe527c6ee827832073509fac4a245ab7 /arch
parent4a34e4b86f75547ff2a546f02196cdfb9439eca4 (diff)
downloadtalos-obmc-uboot-8827227889848433d464f31c76c8be9d13567623.tar.gz
talos-obmc-uboot-8827227889848433d464f31c76c8be9d13567623.zip
x86: minnowmax: add GPIO banks in the device tree
There are 6 banks: 4 banks for CORE: available in S0 mode 2 banks for SUS (Suspend): available in S0-S5 mode Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/dts/minnowmax.dts42
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index ecd4a892c0..4be227a3b0 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -22,6 +22,48 @@
silent_console = <0>;
};
+ gpioa {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0 0x20>;
+ bank-name = "A";
+ };
+
+ gpiob {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x20 0x20>;
+ bank-name = "B";
+ };
+
+ gpioc {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x40 0x20>;
+ bank-name = "C";
+ };
+
+ gpiod {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x60 0x20>;
+ bank-name = "D";
+ };
+
+ gpioe {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0x80 0x20>;
+ bank-name = "E";
+ };
+
+ gpiof {
+ compatible = "intel,ich6-gpio";
+ u-boot,dm-pre-reloc;
+ reg = <0xA0 0x20>;
+ bank-name = "F";
+ };
+
chosen {
stdout-path = "/serial";
};
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