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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-04-27 14:16:02 +0800 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-04-29 18:51:50 -0600 |
| commit | f82a7840f11d008f06b8c8d5578d2f4b8eeaa285 (patch) | |
| tree | 1d3e5884e42eaacf7e62820359b7380ff6d0bc33 /arch/x86 | |
| parent | 283a08e52a0d3f5fe8ac3139c632f32a03fc44f0 (diff) | |
| download | talos-obmc-uboot-f82a7840f11d008f06b8c8d5578d2f4b8eeaa285.tar.gz talos-obmc-uboot-f82a7840f11d008f06b8c8d5578d2f4b8eeaa285.zip | |
x86: quark: Turn on legacy segments decode
By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in the F segment.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/quark/quark.c | 12 | ||||
| -rw-r--r-- | arch/x86/include/asm/arch-quark/quark.h | 7 |
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index e4b19c2759..4ffa4373ab 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -72,6 +72,15 @@ static void quark_setup_bars(void) CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); } +static void quark_enable_legacy_seg(void) +{ + u32 hmisc2; + + hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2); + hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB); + msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2); +} + int arch_cpu_init(void) { struct pci_controller *hose; @@ -96,6 +105,9 @@ int arch_cpu_init(void) */ quark_setup_bars(); + /* Turn on legacy segments (A/B/E/F) decode to system RAM */ + quark_enable_legacy_seg(); + unprotect_spi_flash(); return 0; diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h index ceb583e3f0..6dd02fd31e 100644 --- a/arch/x86/include/asm/arch-quark/quark.h +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -21,6 +21,13 @@ /* Port 0x03: Host Bridge Message Port Registers */ +/* Host Miscellaneous Controls 2 */ +#define HMISC2 0x03 + +#define HMISC2_SEGE 0x00000002 +#define HMISC2_SEGF 0x00000004 +#define HMISC2_SEGAB 0x00000010 + /* Host Memory I/O Boundary */ #define HM_BOUND 0x08 |
