x86: Support platform PIRQ routing

On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).

We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

1 files changed, 31 insertions, 0 deletions

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 3f1401ae4d..aaceaef8b5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -442,6 +442,37 @@ config TSC_FREQ_IN_MHZ
 	help
 	  The running frequency in MHz of Time-Stamp Counter (TSC).
 
+menu "System tables"
+
+config GENERATE_PIRQ_TABLE
+	bool "Generate a PIRQ table"
+	default n
+	help
+	  Generate a PIRQ routing table for this board. The PIRQ routing table
+	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
+	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
+	  It specifies the interrupt router information as well how all the PCI
+	  devices' interrupt pins are wired to PIRQs.
+
+endmenu
+
+config MAX_PIRQ_LINKS
+	int
+	default 8
+	help
+	  This variable specifies the number of PIRQ interrupt links which are
+	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
+	  Some newer chipsets offer more than four links, commonly up to PIRQH.
+
+config IRQ_SLOT_COUNT
+	int
+	default 128
+	help
+	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
+	  which in turns forms a table of exact 4KiB. The default value 128
+	  should be enough for most boards. If this does not fit your board,
+	  change it according to your needs.
+
 source "board/coreboot/coreboot/Kconfig"
 
 source "board/google/chromebook_link/Kconfig"