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authormario.six@gdsys.cc <mario.six@gdsys.cc>2016-04-05 15:05:37 +0200
committerYork Sun <york.sun@nxp.com>2016-04-08 15:42:10 -0700
commit50689461205e0125759eb1a43787383a3fa09b48 (patch)
tree00deec51ae3651b7c7544c20cdef3610226661cd /arch/powerpc
parentb39d1213e30717c435c8ed43411d573d435557cb (diff)
downloadtalos-obmc-uboot-50689461205e0125759eb1a43787383a3fa09b48.tar.gz
talos-obmc-uboot-50689461205e0125759eb1a43787383a3fa09b48.zip
powerpc: mpc85xx: Enable pre-relocation malloc for MPC85xx
To enable DM on MPC85xx, we need pre-relocation malloc, which is implemented in this patch. We also make sure that the IVORs are always 4-aligned on e500 to prevent alignment exceptions caused by code changes in start.S. Signed-off-by: Mario Six <mario.six@gdsys.cc> Cc: York Sun <york.sun@nxp.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init_early.c9
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S30
2 files changed, 32 insertions, 7 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 235a635c22..aa519b03fe 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -82,7 +82,6 @@ void setup_ifc(void)
void cpu_init_early_f(void *fdt)
{
u32 mas0, mas1, mas2, mas3, mas7;
- int i;
#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
@@ -90,17 +89,13 @@ void cpu_init_early_f(void *fdt)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
u32 *dst, *src;
void (*setup_ifc_sram)(void);
+ int i;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
- /*
- * Clear initial global data
- * we don't use memset so we can share this code with NAND_SPL
- */
- for (i = 0; i < sizeof(gd_t); i++)
- ((char *)gd)[i] = 0;
+ /* gd area was zeroed during startup */
#ifdef CONFIG_QEMU_E500
/*
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index d867e2a767..82a151a0d0 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1152,6 +1152,36 @@ _start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h
ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+
+#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE
+#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM."
+#endif
+
+ /* Leave 16+ byte for back chain termination and NULL return address */
+ subi r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf)
+#endif
+
+ /* End of RAM */
+ lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+ ori r4,r4,(CONFIG_SYS_INIT_RAM_SIZE)@l
+
+ li r0,0
+
+1: subi r4,r4,4
+ stw r0,0(r4)
+ cmplw r4,r3
+ bne 1b
+
+#ifdef CONFIG_SYS_MALLOC_F_LEN
+ lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h
+ ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+ addi r3,r3,16 /* Pre-relocation malloc area */
+ stw r3,GD_MALLOC_BASE(r4)
+ subi r3,r3,16
+#endif
li r0,0
stw r0,0(r3) /* Terminate Back Chain */
stw r0,+4(r3) /* NULL return address. */
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