powerpc: Fix CamelCase warnings in DDR related code

Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl

Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>

13 files changed, 464 insertions, 464 deletions

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
index 06706ed78c..17d8d9f740 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/common_timing_params.h
@@ -12,39 +12,39 @@
 typedef struct {
 	/* parameters to constrict */
 
-	unsigned int tCKmin_X_ps;
-	unsigned int tCKmax_ps;
-	unsigned int tCKmax_max_ps;
-	unsigned int tRCD_ps;
-	unsigned int tRP_ps;
-	unsigned int tRAS_ps;
-
-	unsigned int tWR_ps;	/* maximum = 63750 ps */
-	unsigned int tWTR_ps;	/* maximum = 63750 ps */
-	unsigned int tRFC_ps;	/* maximum = 255 ns + 256 ns + .75 ns
+	unsigned int tckmin_x_ps;
+	unsigned int tckmax_ps;
+	unsigned int tckmax_max_ps;
+	unsigned int trcd_ps;
+	unsigned int trp_ps;
+	unsigned int tras_ps;
+
+	unsigned int twr_ps;	/* maximum = 63750 ps */
+	unsigned int twtr_ps;	/* maximum = 63750 ps */
+	unsigned int trfc_ps;	/* maximum = 255 ns + 256 ns + .75 ns
 					   = 511750 ps */
 
-	unsigned int tRRD_ps;	/* maximum = 63750 ps */
-	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+	unsigned int trrd_ps;	/* maximum = 63750 ps */
+	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 
 	unsigned int refresh_rate_ps;
 
-	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
-	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
-	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
-	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
-	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
-	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
-	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
+	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tds_ps;	/* byte 34, spd->data_setup */
+	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
+	unsigned int trtp_ps;	/* byte 38, spd->trtp */
+	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
 
 	unsigned int ndimms_present;
 	unsigned int lowest_common_SPD_caslat;
 	unsigned int highest_common_derated_caslat;
 	unsigned int additive_latency;
-	unsigned int all_DIMMs_burst_lengths_bitmask;
-	unsigned int all_DIMMs_registered;
-	unsigned int all_DIMMs_unbuffered;
-	unsigned int all_DIMMs_ECC_capable;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
+	unsigned int all_dimms_ecc_capable;
 
 	unsigned long long total_mem;
 	unsigned long long base_address;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 242eb47ac3..d7333ba3dd 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -353,14 +353,14 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
 	/* Control Adjust */
 	unsigned int cntl_adj = 0;
 
-	ext_pretoact = picos_to_mclk(common_dimm->tRP_ps) >> 4;
-	ext_acttopre = picos_to_mclk(common_dimm->tRAS_ps) >> 4;
-	ext_acttorw = picos_to_mclk(common_dimm->tRCD_ps) >> 4;
+	ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4;
+	ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4;
+	ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4;
 	ext_caslat = (2 * cas_latency - 1) >> 4;
-	ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
+	ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4;
 	/* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
-	ext_wrrec = (picos_to_mclk(common_dimm->tWR_ps) +
-		(popts->OTF_burst_chop_en ? 2 : 0)) >> 4;
+	ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) +
+		(popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 
 	ddr->timing_cfg_3 = (0
 		| ((ext_pretoact & 0x1) << 28)
@@ -400,9 +400,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 	static const u8 wrrec_table[] = {
 		1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 
-	pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
-	acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
-	acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
+	pretoact_mclk = picos_to_mclk(common_dimm->trp_ps);
+	acttopre_mclk = picos_to_mclk(common_dimm->tras_ps);
+	acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps);
 
 	/*
 	 * Translate CAS Latency to a DDR controller field value:
@@ -433,17 +433,17 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 	caslat_ctrl = 2 * cas_latency - 1;
 #endif
 
-	refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
-	wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
+	refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8;
+	wrrec_mclk = picos_to_mclk(common_dimm->twr_ps);
 
 	if (wrrec_mclk > 16)
 		printf("Error: WRREC doesn't support more than 16 clocks\n");
 	else
 		wrrec_mclk = wrrec_table[wrrec_mclk - 1];
-	if (popts->OTF_burst_chop_en)
+	if (popts->otf_burst_chop_en)
 		wrrec_mclk += 2;
 
-	acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
+	acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps);
 	/*
 	 * JEDEC has min requirement for tRRD
 	 */
@@ -451,7 +451,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 	if (acttoact_mclk < 4)
 		acttoact_mclk = 4;
 #endif
-	wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
+	wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps);
 	/*
 	 * JEDEC has some min requirements for tWTR
 	 */
@@ -462,7 +462,7 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 	if (wrtord_mclk < 4)
 		wrtord_mclk = 4;
 #endif
-	if (popts->OTF_burst_chop_en)
+	if (popts->otf_burst_chop_en)
 		wrtord_mclk += 2;
 
 	ddr->timing_cfg_1 = (0
@@ -518,7 +518,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	wr_lat = compute_cas_write_latency();
 #endif
 
-	rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
+	rd_to_pre = picos_to_mclk(common_dimm->trtp_ps);
 	/*
 	 * JEDEC has some min requirements for tRTP
 	 */
@@ -531,12 +531,12 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 #endif
 	if (additive_latency)
 		rd_to_pre += additive_latency;
-	if (popts->OTF_burst_chop_en)
+	if (popts->otf_burst_chop_en)
 		rd_to_pre += 2; /* according to UM */
 
 	wr_data_delay = popts->write_data_delay;
-	cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
-	four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
+	cke_pls = picos_to_mclk(popts->tcke_clock_pulse_width_ps);
+	four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps);
 
 	ddr->timing_cfg_2 = (0
 		| ((add_lat_mclk & 0xf) << 28)
@@ -555,8 +555,8 @@ static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 			       const memctl_options_t *popts,
 			       const common_timing_params_t *common_dimm)
 {
-	if (common_dimm->all_DIMMs_registered
-		&& !common_dimm->all_DIMMs_unbuffered) {
+	if (common_dimm->all_dimms_registered &&
+	    !common_dimm->all_dimms_unbuffered)	{
 		if (popts->rcw_override) {
 			ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 			ddr->ddr_sdram_rcw_2 = popts->rcw_2;
@@ -599,8 +599,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int dbw;		/* DRAM dta bus width */
 	unsigned int eight_be = 0;	/* 8-beat burst enable, DDR2 is zero */
 	unsigned int ncap = 0;		/* Non-concurrent auto-precharge */
-	unsigned int threeT_en;		/* Enable 3T timing */
-	unsigned int twoT_en;		/* Enable 2T timing */
+	unsigned int threet_en;		/* Enable 3T timing */
+	unsigned int twot_en;		/* Enable 2T timing */
 	unsigned int ba_intlv_ctl;	/* Bank (CS) interleaving control */
 	unsigned int x32_en = 0;	/* x32 enable */
 	unsigned int pchb8 = 0;		/* precharge bit 8 enable */
@@ -610,20 +610,20 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 
 	mem_en = 1;
 	sren = popts->self_refresh_in_sleep;
-	if (common_dimm->all_DIMMs_ECC_capable) {
+	if (common_dimm->all_dimms_ecc_capable) {
 		/* Allow setting of ECC only if all DIMMs are ECC. */
-		ecc_en = popts->ECC_mode;
+		ecc_en = popts->ecc_mode;
 	} else {
 		ecc_en = 0;
 	}
 
-	if (common_dimm->all_DIMMs_registered
-		&& !common_dimm->all_DIMMs_unbuffered) {
+	if (common_dimm->all_dimms_registered &&
+	    !common_dimm->all_dimms_unbuffered)	{
 		rd_en = 1;
-		twoT_en = 0;
+		twot_en = 0;
 	} else {
 		rd_en = 0;
-		twoT_en = popts->twoT_en;
+		twot_en = popts->twot_en;
 	}
 
 	sdram_type = CONFIG_FSL_SDRAM_TYPE;
@@ -643,7 +643,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 			eight_be = 1;
 	}
 
-	threeT_en = popts->threeT_en;
+	threet_en = popts->threet_en;
 	ba_intlv_ctl = popts->ba_intlv_ctl;
 	hse = popts->half_strength_driver_enable;
 
@@ -657,8 +657,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 			| ((dbw & 0x3) << 19)
 			| ((eight_be & 0x1) << 18)
 			| ((ncap & 0x1) << 17)
-			| ((threeT_en & 0x1) << 16)
-			| ((twoT_en & 0x1) << 15)
+			| ((threet_en & 0x1) << 16)
+			| ((twot_en & 0x1) << 15)
 			| ((ba_intlv_ctl & 0x7F) << 8)
 			| ((x32_en & 0x1) << 5)
 			| ((pchb8 & 0x1) << 4)
@@ -691,7 +691,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	int i;
 
 	dll_rst_dis = 1;	/* Make this configurable */
-	dqs_cfg = popts->DQS_config;
+	dqs_cfg = popts->dqs_config;
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (popts->cs_local_opts[i].odt_rd_cfg
 			|| popts->cs_local_opts[i].odt_wr_cfg) {
@@ -710,7 +710,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	 *      << DDR_SDRAM_INTERVAL[REFINT]
 	 */
 #if defined(CONFIG_FSL_DDR3)
-	obc_cfg = popts->OTF_burst_chop_en;
+	obc_cfg = popts->otf_burst_chop_en;
 #else
 	obc_cfg = 0;
 #endif
@@ -730,7 +730,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	/* Use the DDR controller to auto initialize memory. */
-	d_init = popts->ECC_init_using_memctl;
+	d_init = popts->ecc_init_using_memctl;
 	ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 	debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 #else
@@ -939,7 +939,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	 */
 	dll_on = 1;
 
-	wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
+	wr_mclk = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps;
 	if (wr_mclk <= 16) {
 		wr = wr_table[wr_mclk - 5];
 	} else {
@@ -1101,7 +1101,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_FSL_DDR2)
 	const unsigned int mclk_ps = get_memory_clk_period_ps();
 #endif
-	dqs_en = !popts->DQS_config;
+	dqs_en = !popts->dqs_config;
 	rtt = fsl_ddr_get_rtt();
 
 	al = additive_latency;
@@ -1130,7 +1130,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_FSL_DDR1)
 	wr = 0;       /* Historical */
 #elif defined(CONFIG_FSL_DDR2)
-	wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
+	wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
 #endif
 	dll_res = 0;
 	mode = 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index c173a5a74b..e3b414e666 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -72,7 +72,7 @@ unsigned int compute_lowest_common_dimm_parameters(
 				const dimm_params_t *dimm_params,
 				common_timing_params_t *outpdimm,
 				unsigned int number_of_dimms);
-unsigned int populate_memctl_options(int all_DIMMs_registered,
+unsigned int populate_memctl_options(int all_dimms_registered,
 				memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
index 376be2fb37..f137fcee34 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr1_dimm_params.c
@@ -287,57 +287,57 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd,
 	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
 	 * nanoseconds and represented as BCD.
 	 */
-	pdimm->tCKmin_X_ps
+	pdimm->tckmin_x_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
-	pdimm->tCKmin_X_minus_1_ps
+	pdimm->tckmin_x_minus_1_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
-	pdimm->tCKmin_X_minus_2_ps
+	pdimm->tckmin_x_minus_2_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
 
-	pdimm->tCKmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
+	pdimm->tckmax_ps = compute_tckmax_from_spd_ps(spd->tckmax);
 
 	/*
 	 * Compute CAS latencies defined by SPD
-	 * The SPD caslat_X should have at least 1 and at most 3 bits set.
+	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
 	 *
 	 * If cas_lat after masking is 0, the __ilog2 function returns
 	 * 255 into the variable.   This behavior is abused once.
 	 */
-	pdimm->caslat_X  = __ilog2(spd->cas_lat);
-	pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X));
-	pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X)
-					  & ~(1 << pdimm->caslat_X_minus_1));
+	pdimm->caslat_x  = __ilog2(spd->cas_lat);
+	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x));
+	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x)
+					  & ~(1 << pdimm->caslat_x_minus_1));
 
 	/* Compute CAS latencies below that defined by SPD */
 	pdimm->caslat_lowest_derated
 		= compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps());
 
 	/* Compute timing parameters */
-	pdimm->tRCD_ps = spd->trcd * 250;
-	pdimm->tRP_ps = spd->trp * 250;
-	pdimm->tRAS_ps = spd->tras * 1000;
+	pdimm->trcd_ps = spd->trcd * 250;
+	pdimm->trp_ps = spd->trp * 250;
+	pdimm->tras_ps = spd->tras * 1000;
 
-	pdimm->tWR_ps = mclk_to_picos(3);
-	pdimm->tWTR_ps = mclk_to_picos(1);
-	pdimm->tRFC_ps = compute_trfc_ps_from_spd(0, spd->trfc);
+	pdimm->twr_ps = mclk_to_picos(3);
+	pdimm->twtr_ps = mclk_to_picos(1);
+	pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc);
 
-	pdimm->tRRD_ps = spd->trrd * 250;
-	pdimm->tRC_ps = compute_trc_ps_from_spd(0, spd->trc);
+	pdimm->trrd_ps = spd->trrd * 250;
+	pdimm->trc_ps = compute_trc_ps_from_spd(0, spd->trc);
 
 	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
 
-	pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
-	pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
-	pdimm->tDS_ps
+	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
+	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
+	pdimm->tds_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
-	pdimm->tDH_ps
+	pdimm->tdh_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
 
-	pdimm->tRTP_ps = mclk_to_picos(2);	/* By the book. */
-	pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
-	pdimm->tQHS_ps = spd->tqhs * 10;
+	pdimm->trtp_ps = mclk_to_picos(2);	/* By the book. */
+	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
+	pdimm->tqhs_ps = spd->tqhs * 10;
 
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
index f637f3d045..e4d02e8f61 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c
@@ -286,57 +286,57 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
 	 * The SPD clk_cycle field (tCKmin) is measured in tenths of
 	 * nanoseconds and represented as BCD.
 	 */
-	pdimm->tCKmin_X_ps
+	pdimm->tckmin_x_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
-	pdimm->tCKmin_X_minus_1_ps
+	pdimm->tckmin_x_minus_1_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
-	pdimm->tCKmin_X_minus_2_ps
+	pdimm->tckmin_x_minus_2_ps
 		= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
 
-	pdimm->tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
+	pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
 
 	/*
 	 * Compute CAS latencies defined by SPD
-	 * The SPD caslat_X should have at least 1 and at most 3 bits set.
+	 * The SPD caslat_x should have at least 1 and at most 3 bits set.
 	 *
 	 * If cas_lat after masking is 0, the __ilog2 function returns
 	 * 255 into the variable.   This behavior is abused once.
 	 */
-	pdimm->caslat_X  = __ilog2(spd->cas_lat);
-	pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X));
-	pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat
-					  & ~(1 << pdimm->caslat_X)
-					  & ~(1 << pdimm->caslat_X_minus_1));
+	pdimm->caslat_x  = __ilog2(spd->cas_lat);
+	pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x));
+	pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
+					  & ~(1 << pdimm->caslat_x)
+					  & ~(1 << pdimm->caslat_x_minus_1));
 
 	/* Compute CAS latencies below that defined by SPD */
 	pdimm->caslat_lowest_derated
 		= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
 
 	/* Compute timing parameters */
-	pdimm->tRCD_ps = spd->trcd * 250;
-	pdimm->tRP_ps = spd->trp * 250;
-	pdimm->tRAS_ps = spd->tras * 1000;
+	pdimm->trcd_ps = spd->trcd * 250;
+	pdimm->trp_ps = spd->trp * 250;
+	pdimm->tras_ps = spd->tras * 1000;
 
-	pdimm->tWR_ps = spd->twr * 250;
-	pdimm->tWTR_ps = spd->twtr * 250;
-	pdimm->tRFC_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
+	pdimm->twr_ps = spd->twr * 250;
+	pdimm->twtr_ps = spd->twtr * 250;
+	pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
 
-	pdimm->tRRD_ps = spd->trrd * 250;
-	pdimm->tRC_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
+	pdimm->trrd_ps = spd->trrd * 250;
+	pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
 
 	pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
 
-	pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
-	pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
-	pdimm->tDS_ps
+	pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
+	pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
+	pdimm->tds_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
-	pdimm->tDH_ps
+	pdimm->tdh_ps
 		= convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
 
-	pdimm->tRTP_ps = spd->trtp * 250;
-	pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
-	pdimm->tQHS_ps = spd->tqhs * 10;
+	pdimm->trtp_ps = spd->trtp * 250;
+	pdimm->tdqsq_max_ps = spd->tdqsq * 10;
+	pdimm->tqhs_ps = spd->tqhs * 10;
 
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index b67158c0ff..d82eb674d3 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -210,12 +210,12 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	 * sdram minimum cycle time
 	 * we assume the MTB is 0.125ns
 	 * eg:
-	 * tCK_min=15 MTB (1.875ns) ->DDR3-1066
+	 * tck_min=15 MTB (1.875ns) ->DDR3-1066
 	 *        =12 MTB (1.5ns) ->DDR3-1333
 	 *        =10 MTB (1.25ns) ->DDR3-1600
 	 */
-	pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps +
-		(spd->fine_tCK_min * ftb_10th_ps) / 10;
+	pdimm->tckmin_x_ps = spd->tck_min * mtb_ps +
+		(spd->fine_tck_min * ftb_10th_ps) / 10;
 
 	/*
 	 * CAS latency supported
@@ -223,55 +223,55 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	 * bit5 - CL5
 	 * bit18 - CL18
 	 */
-	pdimm->caslat_X  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
+	pdimm->caslat_x  = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
 
 	/*
 	 * min CAS latency time
-	 * eg: tAA_min =
+	 * eg: taa_min =
 	 * DDR3-800D	100 MTB (12.5ns)
 	 * DDR3-1066F	105 MTB (13.125ns)
 	 * DDR3-1333H	108 MTB (13.5ns)
 	 * DDR3-1600H	90 MTB (11.25ns)
 	 */
-	pdimm->tAA_ps = spd->tAA_min * mtb_ps +
-		(spd->fine_tAA_min * ftb_10th_ps) / 10;
+	pdimm->taa_ps = spd->taa_min * mtb_ps +
+		(spd->fine_taa_min * ftb_10th_ps) / 10;
 
 	/*
 	 * min write recovery time
 	 * eg:
-	 * tWR_min = 120 MTB (15ns) -> all speed grades.
+	 * twr_min = 120 MTB (15ns) -> all speed grades.
 	 */
-	pdimm->tWR_ps = spd->tWR_min * mtb_ps;
+	pdimm->twr_ps = spd->twr_min * mtb_ps;
 
 	/*
 	 * min RAS to CAS delay time
-	 * eg: tRCD_min =
+	 * eg: trcd_min =
 	 * DDR3-800	100 MTB (12.5ns)
 	 * DDR3-1066F	105 MTB (13.125ns)
 	 * DDR3-1333H	108 MTB (13.5ns)
 	 * DDR3-1600H	90 MTB (11.25)
 	 */
-	pdimm->tRCD_ps = spd->tRCD_min * mtb_ps +
-		(spd->fine_tRCD_min * ftb_10th_ps) / 10;
+	pdimm->trcd_ps = spd->trcd_min * mtb_ps +
+		(spd->fine_trcd_min * ftb_10th_ps) / 10;
 
 	/*
 	 * min row active to row active delay time
-	 * eg: tRRD_min =
+	 * eg: trrd_min =
 	 * DDR3-800(1KB page)	80 MTB (10ns)
 	 * DDR3-1333(1KB page)	48 MTB (6ns)
 	 */
-	pdimm->tRRD_ps = spd->tRRD_min * mtb_ps;
+	pdimm->trrd_ps = spd->trrd_min * mtb_ps;
 
 	/*
 	 * min row precharge delay time
-	 * eg: tRP_min =
+	 * eg: trp_min =
 	 * DDR3-800D	100 MTB (12.5ns)
 	 * DDR3-1066F	105 MTB (13.125ns)
 	 * DDR3-1333H	108 MTB (13.5ns)
 	 * DDR3-1600H	90 MTB (11.25ns)
 	 */
-	pdimm->tRP_ps = spd->tRP_min * mtb_ps +
-		(spd->fine_tRP_min * ftb_10th_ps) / 10;
+	pdimm->trp_ps = spd->trp_min * mtb_ps +
+		(spd->fine_trp_min * ftb_10th_ps) / 10;
 
 	/* min active to precharge delay time
 	 * eg: tRAS_min =
@@ -280,7 +280,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	 * DDR3-1333H	288 MTB (36ns)
 	 * DDR3-1600H	280 MTB (35ns)
 	 */
-	pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb)
+	pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) | spd->tras_min_lsb)
 			* mtb_ps;
 	/*
 	 * min active to actice/refresh delay time
@@ -290,8 +290,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	 * DDR3-1333H	396 MTB (49.5ns)
 	 * DDR3-1600H	370 MTB (46.25ns)
 	 */
-	pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb)
-			* mtb_ps + (spd->fine_tRC_min * ftb_10th_ps) / 10;
+	pdimm->trc_ps = (((spd->tras_trc_ext & 0xf0) << 4) | spd->trc_min_lsb)
+			* mtb_ps + (spd->fine_trc_min * ftb_10th_ps) / 10;
 	/*
 	 * min refresh recovery delay time
 	 * eg: tRFC_min =
@@ -299,21 +299,21 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	 * 1Gb		880 MTB (110ns)
 	 * 2Gb		1280 MTB (160ns)
 	 */
-	pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb)
+	pdimm->trfc_ps = ((spd->trfc_min_msb << 8) | spd->trfc_min_lsb)
 			* mtb_ps;
 	/*
 	 * min internal write to read command delay time
-	 * eg: tWTR_min = 40 MTB (7.5ns) - all speed bins.
+	 * eg: twtr_min = 40 MTB (7.5ns) - all speed bins.
 	 * tWRT is at least 4 mclk independent of operating freq.
 	 */
-	pdimm->tWTR_ps = spd->tWTR_min * mtb_ps;
+	pdimm->twtr_ps = spd->twtr_min * mtb_ps;
 
 	/*
 	 * min internal read to precharge command delay time
-	 * eg: tRTP_min = 40 MTB (7.5ns) - all speed bins.
+	 * eg: trtp_min = 40 MTB (7.5ns) - all speed bins.
 	 * tRTP is at least 4 mclk independent of operating freq.
 	 */
-	pdimm->tRTP_ps = spd->tRTP_min * mtb_ps;
+	pdimm->trtp_ps = spd->trtp_min * mtb_ps;
 
 	/*
 	 * Average periodic refresh interval
@@ -324,13 +324,13 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 
 	/*
 	 * min four active window delay time
-	 * eg: tFAW_min =
+	 * eg: tfaw_min =
 	 * DDR3-800(1KB page)	320 MTB (40ns)
 	 * DDR3-1066(1KB page)	300 MTB (37.5ns)
 	 * DDR3-1333(1KB page)	240 MTB (30ns)
 	 * DDR3-1600(1KB page)	240 MTB (30ns)
 	 */
-	pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min)
+	pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min)
 			* mtb_ps;
 
 	return 0;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index 260fce577f..3b661129cb 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -150,33 +150,33 @@ static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 	common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
 
 	static const struct options_string options[] = {
-		COMMON_TIMING(tCKmin_X_ps),
-		COMMON_TIMING(tCKmax_ps),
-		COMMON_TIMING(tCKmax_max_ps),
-		COMMON_TIMING(tRCD_ps),
-		COMMON_TIMING(tRP_ps),
-		COMMON_TIMING(tRAS_ps),
-		COMMON_TIMING(tWR_ps),
-		COMMON_TIMING(tWTR_ps),
-		COMMON_TIMING(tRFC_ps),
-		COMMON_TIMING(tRRD_ps),
-		COMMON_TIMING(tRC_ps),
+		COMMON_TIMING(tckmin_x_ps),
+		COMMON_TIMING(tckmax_ps),
+		COMMON_TIMING(tckmax_max_ps),
+		COMMON_TIMING(trcd_ps),
+		COMMON_TIMING(trp_ps),
+		COMMON_TIMING(tras_ps),
+		COMMON_TIMING(twr_ps),
+		COMMON_TIMING(twtr_ps),
+		COMMON_TIMING(trfc_ps),
+		COMMON_TIMING(trrd_ps),
+		COMMON_TIMING(trc_ps),
 		COMMON_TIMING(refresh_rate_ps),
-		COMMON_TIMING(tIS_ps),
-		COMMON_TIMING(tIH_ps),
-		COMMON_TIMING(tDS_ps),
-		COMMON_TIMING(tDH_ps),
-		COMMON_TIMING(tRTP_ps),
-		COMMON_TIMING(tDQSQ_max_ps),
-		COMMON_TIMING(tQHS_ps),
+		COMMON_TIMING(tis_ps),
+		COMMON_TIMING(tih_ps),
+		COMMON_TIMING(tds_ps),
+		COMMON_TIMING(tdh_ps),
+		COMMON_TIMING(trtp_ps),
+		COMMON_TIMING(tdqsq_max_ps),
+		COMMON_TIMING(tqhs_ps),
 		COMMON_TIMING(ndimms_present),
 		COMMON_TIMING(lowest_common_SPD_caslat),
 		COMMON_TIMING(highest_common_derated_caslat),
 		COMMON_TIMING(additive_latency),
-		COMMON_TIMING(all_DIMMs_burst_lengths_bitmask),
-		COMMON_TIMING(all_DIMMs_registered),
-		COMMON_TIMING(all_DIMMs_unbuffered),
-		COMMON_TIMING(all_DIMMs_ECC_capable),
+		COMMON_TIMING(all_dimms_burst_lengths_bitmask),
+		COMMON_TIMING(all_dimms_registered),
+		COMMON_TIMING(all_dimms_unbuffered),
+		COMMON_TIMING(all_dimms_ecc_capable),
 		COMMON_TIMING(total_mem),
 		COMMON_TIMING(base_address),
 	};
@@ -214,34 +214,34 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
 		DIMM_PARM(burst_lengths_bitmask),
 		DIMM_PARM(row_density),
 
-		DIMM_PARM(tCKmin_X_ps),
-		DIMM_PARM(tCKmin_X_minus_1_ps),
-		DIMM_PARM(tCKmin_X_minus_2_ps),
-		DIMM_PARM(tCKmax_ps),
+		DIMM_PARM(tckmin_x_ps),
+		DIMM_PARM(tckmin_x_minus_1_ps),
+		DIMM_PARM(tckmin_x_minus_2_ps),
+		DIMM_PARM(tckmax_ps),
 
-		DIMM_PARM(caslat_X),
-		DIMM_PARM(caslat_X_minus_1),
-		DIMM_PARM(caslat_X_minus_2),
+		DIMM_PARM(caslat_x),
+		DIMM_PARM(caslat_x_minus_1),
+		DIMM_PARM(caslat_x_minus_2),
 
 		DIMM_PARM(caslat_lowest_derated),
 
-		DIMM_PARM(tRCD_ps),
-		DIMM_PARM(tRP_ps),
-		DIMM_PARM(tRAS_ps),
-		DIMM_PARM(tWR_ps),
-		DIMM_PARM(tWTR_ps),
-		DIMM_PARM(tRFC_ps),
-		DIMM_PARM(tRRD_ps),
-		DIMM_PARM(tRC_ps),
+		DIMM_PARM(trcd_ps),
+		DIMM_PARM(trp_ps),
+		DIMM_PARM(tras_ps),
+		DIMM_PARM(twr_ps),
+		DIMM_PARM(twtr_ps),
+		DIMM_PARM(trfc_ps),
+		DIMM_PARM(trrd_ps),
+		DIMM_PARM(trc_ps),
 		DIMM_PARM(refresh_rate_ps),
 
-		DIMM_PARM(tIS_ps),
-		DIMM_PARM(tIH_ps),
-		DIMM_PARM(tDS_ps),
-		DIMM_PARM(tDH_ps),
-		DIMM_PARM(tRTP_ps),
-		DIMM_PARM(tDQSQ_max_ps),
-		DIMM_PARM(tQHS_ps),
+		DIMM_PARM(tis_ps),
+		DIMM_PARM(tih_ps),
+		DIMM_PARM(tds_ps),
+		DIMM_PARM(tdh_ps),
+		DIMM_PARM(trtp_ps),
+		DIMM_PARM(tdqsq_max_ps),
+		DIMM_PARM(tqhs_ps),
 
 		DIMM_PARM(rank_density),
 		DIMM_PARM(capacity),
@@ -271,34 +271,34 @@ static void print_dimm_parameters(const dimm_params_t *pdimm)
 		DIMM_PARM(edc_config),
 		DIMM_PARM(n_banks_per_sdram_device),
 
-		DIMM_PARM(tCKmin_X_ps),
-		DIMM_PARM(tCKmin_X_minus_1_ps),
-		DIMM_PARM(tCKmin_X_minus_2_ps),
-		DIMM_PARM(tCKmax_ps),
+		DIMM_PARM(tckmin_x_ps),
+		DIMM_PARM(tckmin_x_minus_1_ps),
+		DIMM_PARM(tckmin_x_minus_2_ps),
+		DIMM_PARM(tckmax_ps),
 
-		DIMM_PARM(caslat_X),
-		DIMM_PARM(tAA_ps),
-		DIMM_PARM(caslat_X_minus_1),
-		DIMM_PARM(caslat_X_minus_2),
+		DIMM_PARM(caslat_x),
+		DIMM_PARM(taa_ps),
+		DIMM_PARM(caslat_x_minus_1),
+		DIMM_PARM(caslat_x_minus_2),
 		DIMM_PARM(caslat_lowest_derated),
 
-		DIMM_PARM(tRCD_ps),
-		DIMM_PARM(tRP_ps),
-		DIMM_PARM(tRAS_ps),
-		DIMM_PARM(tWR_ps),
-		DIMM_PARM(tWTR_ps),
-		DIMM_PARM(tRFC_ps),
-		DIMM_PARM(tRRD_ps),
-		DIMM_PARM(tRC_ps),
+		DIMM_PARM(trcd_ps),
+		DIMM_PARM(trp_ps),
+		DIMM_PARM(tras_ps),
+		DIMM_PARM(twr_ps),
+		DIMM_PARM(twtr_ps),
+		DIMM_PARM(trfc_ps),
+		DIMM_PARM(trrd_ps),
+		DIMM_PARM(trc_ps),
 		DIMM_PARM(refresh_rate_ps),
 
-		DIMM_PARM(tIS_ps),
-		DIMM_PARM(tIH_ps),
-		DIMM_PARM(tDS_ps),
-		DIMM_PARM(tDH_ps),
-		DIMM_PARM(tRTP_ps),
-		DIMM_PARM(tDQSQ_max_ps),
-		DIMM_PARM(tQHS_ps),
+		DIMM_PARM(tis_ps),
+		DIMM_PARM(tih_ps),
+		DIMM_PARM(tds_ps),
+		DIMM_PARM(tdh_ps),
+		DIMM_PARM(trtp_ps),
+		DIMM_PARM(tdqsq_max_ps),
+		DIMM_PARM(tqhs_ps),
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
 
@@ -325,41 +325,41 @@ static void print_lowest_common_dimm_parameters(
 		const common_timing_params_t *plcd_dimm_params)
 {
 	static const struct options_string options[] = {
-		COMMON_TIMING(tCKmax_max_ps),
-		COMMON_TIMING(tRCD_ps),
-		COMMON_TIMING(tRP_ps),
-		COMMON_TIMING(tRAS_ps),
-		COMMON_TIMING(tWR_ps),
-		COMMON_TIMING(tWTR_ps),
-		COMMON_TIMING(tRFC_ps),
-		COMMON_TIMING(tRRD_ps),
-		COMMON_TIMING(tRC_ps),
+		COMMON_TIMING(tckmax_max_ps),
+		COMMON_TIMING(trcd_ps),
+		COMMON_TIMING(trp_ps),
+		COMMON_TIMING(tras_ps),
+		COMMON_TIMING(twr_ps),
+		COMMON_TIMING(twtr_ps),
+		COMMON_TIMING(trfc_ps),
+		COMMON_TIMING(trrd_ps),
+		COMMON_TIMING(trc_ps),
 		COMMON_TIMING(refresh_rate_ps),
-		COMMON_TIMING(tIS_ps),
-		COMMON_TIMING(tDS_ps),
-		COMMON_TIMING(tDH_ps),
-		COMMON_TIMING(tRTP_ps),
-		COMMON_TIMING(tDQSQ_max_ps),
-		COMMON_TIMING(tQHS_ps),
+		COMMON_TIMING(tis_ps),
+		COMMON_TIMING(tds_ps),
+		COMMON_TIMING(tdh_ps),
+		COMMON_TIMING(trtp_ps),
+		COMMON_TIMING(tdqsq_max_ps),
+		COMMON_TIMING(tqhs_ps),
 		COMMON_TIMING(lowest_common_SPD_caslat),
 		COMMON_TIMING(highest_common_derated_caslat),
 		COMMON_TIMING(additive_latency),
 		COMMON_TIMING(ndimms_present),
-		COMMON_TIMING(all_DIMMs_registered),
-		COMMON_TIMING(all_DIMMs_unbuffered),
-		COMMON_TIMING(all_DIMMs_ECC_capable),
+		COMMON_TIMING(all_dimms_registered),
+		COMMON_TIMING(all_dimms_unbuffered),
+		COMMON_TIMING(all_dimms_ecc_capable),
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
 
 	/* Clock frequencies */
-	printf("tCKmin_X_ps = %u (%u MHz)\n",
-	       plcd_dimm_params->tCKmin_X_ps,
-	       picos_to_mhz(plcd_dimm_params->tCKmin_X_ps));
-	printf("tCKmax_ps = %u (%u MHz)\n",
-	       plcd_dimm_params->tCKmax_ps,
-	       picos_to_mhz(plcd_dimm_params->tCKmax_ps));
-	printf("all_DIMMs_burst_lengths_bitmask = %02X\n",
-	       plcd_dimm_params->all_DIMMs_burst_lengths_bitmask);
+	printf("tckmin_x_ps = %u (%u MHz)\n",
+	       plcd_dimm_params->tckmin_x_ps,
+	       picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
+	printf("tckmax_ps = %u (%u MHz)\n",
+	       plcd_dimm_params->tckmax_ps,
+	       picos_to_mhz(plcd_dimm_params->tckmax_ps));
+	printf("all_dimms_burst_lengths_bitmask = %02X\n",
+	       plcd_dimm_params->all_dimms_burst_lengths_bitmask);
 
 	print_option_table(options, n_opts, plcd_dimm_params);
 
@@ -421,9 +421,9 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		CTRL_OPTIONS(memctl_interleaving),
 		CTRL_OPTIONS(memctl_interleaving_mode),
 		CTRL_OPTIONS(ba_intlv_ctl),
-		CTRL_OPTIONS(ECC_mode),
-		CTRL_OPTIONS(ECC_init_using_memctl),
-		CTRL_OPTIONS(DQS_config),
+		CTRL_OPTIONS(ecc_mode),
+		CTRL_OPTIONS(ecc_init_using_memctl),
+		CTRL_OPTIONS(dqs_config),
 		CTRL_OPTIONS(self_refresh_in_sleep),
 		CTRL_OPTIONS(dynamic_power),
 		CTRL_OPTIONS(data_bus_width),
@@ -442,8 +442,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		 * These can probably be changed to 2T_EN and 3T_EN
 		 * (using a leading numerical character) without problem
 		 */
-		CTRL_OPTIONS(twoT_en),
-		CTRL_OPTIONS(threeT_en),
+		CTRL_OPTIONS(twot_en),
+		CTRL_OPTIONS(threet_en),
 		CTRL_OPTIONS(ap_en),
 		CTRL_OPTIONS(x4_en),
 		CTRL_OPTIONS(bstopre),
@@ -455,8 +455,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		CTRL_OPTIONS(rcw_2),
 		CTRL_OPTIONS(ddr_cdr1),
 		CTRL_OPTIONS(ddr_cdr2),
-		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
-		CTRL_OPTIONS(tFAW_window_four_activates_ps),
+		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
+		CTRL_OPTIONS(tfaw_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
 		CTRL_OPTIONS(trwt),
 	};
@@ -666,9 +666,9 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS(memctl_interleaving),
 		CTRL_OPTIONS(memctl_interleaving_mode),
 		CTRL_OPTIONS_HEX(ba_intlv_ctl),
-		CTRL_OPTIONS(ECC_mode),
-		CTRL_OPTIONS(ECC_init_using_memctl),
-		CTRL_OPTIONS(DQS_config),
+		CTRL_OPTIONS(ecc_mode),
+		CTRL_OPTIONS(ecc_init_using_memctl),
+		CTRL_OPTIONS(dqs_config),
 		CTRL_OPTIONS(self_refresh_in_sleep),
 		CTRL_OPTIONS(dynamic_power),
 		CTRL_OPTIONS(data_bus_width),
@@ -686,8 +686,8 @@ static void print_memctl_options(const memctl_options_t *popts)
 		 * These can probably be changed to 2T_EN and 3T_EN
 		 * (using a leading numerical character) without problem
 		 */
-		CTRL_OPTIONS(twoT_en),
-		CTRL_OPTIONS(threeT_en),
+		CTRL_OPTIONS(twot_en),
+		CTRL_OPTIONS(threet_en),
 		CTRL_OPTIONS(registered_dimm_en),
 		CTRL_OPTIONS(ap_en),
 		CTRL_OPTIONS(x4_en),
@@ -700,8 +700,8 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS(rcw_2),
 		CTRL_OPTIONS_HEX(ddr_cdr1),
 		CTRL_OPTIONS_HEX(ddr_cdr2),
-		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
-		CTRL_OPTIONS(tFAW_window_four_activates_ps),
+		CTRL_OPTIONS(tcke_clock_pulse_width_ps),
+		CTRL_OPTIONS(tfaw_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
 		CTRL_OPTIONS(trwt),
 	};
@@ -958,10 +958,10 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
 	       " spd->tqhs,        * 45 Max Read DataHold skew tQHS *");
 	printf("%-3d    : %02x %s\n", 46, spd->pll_relock,
 	       " spd->pll_relock,  * 46 PLL Relock time *");
-	printf("%-3d    : %02x %s\n", 47, spd->Tcasemax,
-	       " spd->Tcasemax,    * 47 Tcasemax *");
-	printf("%-3d    : %02x %s\n", 48, spd->psiTAdram,
-	       " spd->psiTAdram,   * 48 Thermal Resistance of DRAM Package "
+	printf("%-3d    : %02x %s\n", 47, spd->t_casemax,
+	       " spd->t_casemax,    * 47 t_casemax *");
+	printf("%-3d    : %02x %s\n", 48, spd->psi_ta_dram,
+	       " spd->psi_ta_dram,   * 48 Thermal Resistance of DRAM Package "
 	       "from Top (Case) to Ambient (Psi T-A DRAM) *");
 	printf("%-3d    : %02x %s\n", 49, spd->dt0_mode,
 	       " spd->dt0_mode,    * 49 DRAM Case Temperature Rise from "
@@ -996,11 +996,11 @@ void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
 	       " spd->dt7,         * 57 DRAM Case Temperature Rise from "
 	       "Ambient due to Bank Interleave Reads with "
 	       "Auto-Precharge (DT7) *");
-	printf("%-3d    : %02x %s\n", 58, spd->psiTApll,
-	       " spd->psiTApll,    * 58 Thermal Resistance of PLL Package form"
+	printf("%-3d    : %02x %s\n", 58, spd->psi_ta_pll,
+	       " spd->psi_ta_pll,    * 58 Thermal Resistance of PLL Package form"
 	       " Top (Case) to Ambient (Psi T-A PLL) *");
-	printf("%-3d    : %02x %s\n", 59, spd->psiTAreg,
-	       " spd->psiTAreg,    * 59 Thermal Reisitance of Register Package"
+	printf("%-3d    : %02x %s\n", 59, spd->psi_ta_reg,
+	       " spd->psi_ta_reg,    * 59 Thermal Reisitance of Register Package"
 	       " from Top (Case) to Ambient (Psi T-A Register) *");
 	printf("%-3d    : %02x %s\n", 60, spd->dtpllactive,
 	       " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
@@ -1087,43 +1087,43 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
 		"mtb_dividend   Medium Timebase (MTB) Dividend");
 	PRINT_NXS(11, spd->mtb_divisor,
 		"mtb_divisor    Medium Timebase (MTB) Divisor");
-	PRINT_NXS(12, spd->tCK_min,
-		"tCK_min        SDRAM Minimum Cycle Time");
+	PRINT_NXS(12, spd->tck_min,
+		  "tck_min        SDRAM Minimum Cycle Time");
 	PRINT_NXS(13, spd->res_13,
 		"res_13         Reserved");
 	PRINT_NXS(14, spd->caslat_lsb,
 		"caslat_lsb     CAS Latencies Supported, LSB");
 	PRINT_NXS(15, spd->caslat_msb,
 		"caslat_msb     CAS Latencies Supported, MSB");
-	PRINT_NXS(16, spd->tAA_min,
-		"tAA_min        Min CAS Latency Time");
-	PRINT_NXS(17, spd->tWR_min,
-		"tWR_min        Min Write REcovery Time");
-	PRINT_NXS(18, spd->tRCD_min,
-		"tRCD_min       Min RAS# to CAS# Delay Time");
-	PRINT_NXS(19, spd->tRRD_min,
-		"tRRD_min       Min Row Active to Row Active Delay Time");
-	PRINT_NXS(20, spd->tRP_min,
-		"tRP_min        Min Row Precharge Delay Time");
-	PRINT_NXS(21, spd->tRAS_tRC_ext,
-		"tRAS_tRC_ext   Upper Nibbles for tRAS and tRC");
-	PRINT_NXS(22, spd->tRAS_min_lsb,
-		"tRAS_min_lsb   Min Active to Precharge Delay Time, LSB");
-	PRINT_NXS(23, spd->tRC_min_lsb,
-		"tRC_min_lsb    Min Active to Active/Refresh Delay Time, LSB");
-	PRINT_NXS(24, spd->tRFC_min_lsb,
-		"tRFC_min_lsb   Min Refresh Recovery Delay Time LSB");
-	PRINT_NXS(25, spd->tRFC_min_msb,
-		"tRFC_min_msb   Min Refresh Recovery Delay Time MSB");
-	PRINT_NXS(26, spd->tWTR_min,
-		"tWTR_min       Min Internal Write to Read Command Delay Time");
-	PRINT_NXS(27, spd->tRTP_min,
-		"tRTP_min "
-		"Min Internal Read to Precharge Command Delay Time");
-	PRINT_NXS(28, spd->tFAW_msb,
-		"tFAW_msb       Upper Nibble for tFAW");
-	PRINT_NXS(29, spd->tFAW_min,
-		"tFAW_min       Min Four Activate Window Delay Time");
+	PRINT_NXS(16, spd->taa_min,
+		  "taa_min        Min CAS Latency Time");
+	PRINT_NXS(17, spd->twr_min,
+		  "twr_min        Min Write REcovery Time");
+	PRINT_NXS(18, spd->trcd_min,
+		  "trcd_min       Min RAS# to CAS# Delay Time");
+	PRINT_NXS(19, spd->trrd_min,
+		  "trrd_min       Min Row Active to Row Active Delay Time");
+	PRINT_NXS(20, spd->trp_min,
+		  "trp_min        Min Row Precharge Delay Time");
+	PRINT_NXS(21, spd->tras_trc_ext,
+		  "tras_trc_ext   Upper Nibbles for tRAS and tRC");
+	PRINT_NXS(22, spd->tras_min_lsb,
+		  "tras_min_lsb   Min Active to Precharge Delay Time, LSB");
+	PRINT_NXS(23, spd->trc_min_lsb,
+		  "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
+	PRINT_NXS(24, spd->trfc_min_lsb,
+		  "trfc_min_lsb   Min Refresh Recovery Delay Time LSB");
+	PRINT_NXS(25, spd->trfc_min_msb,
+		  "trfc_min_msb   Min Refresh Recovery Delay Time MSB");
+	PRINT_NXS(26, spd->twtr_min,
+		  "twtr_min Min Internal Write to Read Command Delay Time");
+	PRINT_NXS(27, spd->trtp_min,
+		  "trtp_min "
+		  "Min Internal Read to Precharge Command Delay Time");
+	PRINT_NXS(28, spd->tfaw_msb,
+		  "tfaw_msb       Upper Nibble for tFAW");
+	PRINT_NXS(29, spd->tfaw_min,
+		  "tfaw_min       Min Four Activate Window Delay Time");
 	PRINT_NXS(30, spd->opt_features,
 		"opt_features   SDRAM Optional Features");
 	PRINT_NXS(31, spd->therm_ref_opt,
@@ -1132,16 +1132,16 @@ void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
 		"therm_sensor  SDRAM Thermal Sensor");
 	PRINT_NXS(33, spd->device_type,
 		"device_type  SDRAM Device Type");
-	PRINT_NXS(34, spd->fine_tCK_min,
-		"fine_tCK_min  Fine offset for tCKmin");
-	PRINT_NXS(35, spd->fine_tAA_min,
-		"fine_tAA_min  Fine offset for tAAmin");
-	PRINT_NXS(36, spd->fine_tRCD_min,
-		"fine_tRCD_min Fine offset for tRCDmin");
-	PRINT_NXS(37, spd->fine_tRP_min,
-		"fine_tRP_min  Fine offset for tRPmin");
-	PRINT_NXS(38, spd->fine_tRC_min,
-		"fine_tRC_min  Fine offset for tRCmin");
+	PRINT_NXS(34, spd->fine_tck_min,
+		  "fine_tck_min  Fine offset for tCKmin");
+	PRINT_NXS(35, spd->fine_taa_min,
+		  "fine_taa_min  Fine offset for tAAmin");
+	PRINT_NXS(36, spd->fine_trcd_min,
+		  "fine_trcd_min Fine offset for tRCDmin");
+	PRINT_NXS(37, spd->fine_trp_min,
+		  "fine_trp_min  Fine offset for tRPmin");
+	PRINT_NXS(38, spd->fine_trc_min,
+		  "fine_trc_min  Fine offset for tRCmin");
 
 	printf("%-3d-%3d: ",  39, 59);  /* Reserved, General Section */
 
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 56128a7b96..3affcee7df 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -18,8 +18,8 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 			 unsigned int number_of_dimms)
 {
 	unsigned int i;
-	unsigned int tAAmin_ps = 0;
-	unsigned int tCKmin_X_ps = 0;
+	unsigned int taamin_ps = 0;
+	unsigned int tckmin_x_ps = 0;
 	unsigned int common_caslat;
 	unsigned int caslat_actual;
 	unsigned int retry = 16;
@@ -27,26 +27,26 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 	const unsigned int mclk_ps = get_memory_clk_period_ps();
 
 	/* compute the common CAS latency supported between slots */
-	tmp = dimm_params[0].caslat_X;
+	tmp = dimm_params[0].caslat_x;
 	for (i = 1; i < number_of_dimms; i++) {
 		if (dimm_params[i].n_ranks)
-			tmp &= dimm_params[i].caslat_X;
+			tmp &= dimm_params[i].caslat_x;
 	}
 	common_caslat = tmp;
 
 	/* compute the max tAAmin tCKmin between slots */
 	for (i = 0; i < number_of_dimms; i++) {
-		tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
-		tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
+		taamin_ps = max(taamin_ps, dimm_params[i].taa_ps);
+		tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
 	}
 	/* validate if the memory clk is in the range of dimms */
-	if (mclk_ps < tCKmin_X_ps) {
+	if (mclk_ps < tckmin_x_ps) {
 		printf("DDR clock (MCLK cycle %u ps) is faster than "
 			"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
-			mclk_ps, tCKmin_X_ps);
+			mclk_ps, tckmin_x_ps);
 	}
 	/* determine the acutal cas latency */
-	caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
+	caslat_actual = (taamin_ps + mclk_ps - 1) / mclk_ps;
 	/* check if the dimms support the CAS latency */
 	while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
 		caslat_actual++;
@@ -80,25 +80,25 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 {
 	unsigned int i, j;
 
-	unsigned int tCKmin_X_ps = 0;
-	unsigned int tCKmax_ps = 0xFFFFFFFF;
-	unsigned int tCKmax_max_ps = 0;
-	unsigned int tRCD_ps = 0;
-	unsigned int tRP_ps = 0;
-	unsigned int tRAS_ps = 0;
-	unsigned int tWR_ps = 0;
-	unsigned int tWTR_ps = 0;
-	unsigned int tRFC_ps = 0;
-	unsigned int tRRD_ps = 0;
-	unsigned int tRC_ps = 0;
+	unsigned int tckmin_x_ps = 0;
+	unsigned int tckmax_ps = 0xFFFFFFFF;
+	unsigned int tckmax_max_ps = 0;
+	unsigned int trcd_ps = 0;
+	unsigned int trp_ps = 0;
+	unsigned int tras_ps = 0;
+	unsigned int twr_ps = 0;
+	unsigned int twtr_ps = 0;
+	unsigned int trfc_ps = 0;
+	unsigned int trrd_ps = 0;
+	unsigned int trc_ps = 0;
 	unsigned int refresh_rate_ps = 0;
-	unsigned int tIS_ps = 0;
-	unsigned int tIH_ps = 0;
-	unsigned int tDS_ps = 0;
-	unsigned int tDH_ps = 0;
-	unsigned int tRTP_ps = 0;
-	unsigned int tDQSQ_max_ps = 0;
-	unsigned int tQHS_ps = 0;
+	unsigned int tis_ps = 0;
+	unsigned int tih_ps = 0;
+	unsigned int tds_ps = 0;
+	unsigned int tdh_ps = 0;
+	unsigned int trtp_ps = 0;
+	unsigned int tdqsq_max_ps = 0;
+	unsigned int tqhs_ps = 0;
 
 	unsigned int temp1, temp2;
 	unsigned int additive_latency = 0;
@@ -141,39 +141,39 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 		}
 #endif
 		/*
-		 * Find minimum tCKmax_ps to find fastest slow speed,
+		 * Find minimum tckmax_ps to find fastest slow speed,
 		 * i.e., this is the slowest the whole system can go.
 		 */
-		tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
+		tckmax_ps = min(tckmax_ps, dimm_params[i].tckmax_ps);
 
 		/* Either find maximum value to determine slowest
 		 * speed, delay, time, period, etc */
-		tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
-		tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
-		tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
-		tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
-		tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
-		tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
-		tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
-		tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
-		tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
-		tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
-		tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
-		tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
-		tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
-		tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
-		tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
-		tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
+		tckmin_x_ps = max(tckmin_x_ps, dimm_params[i].tckmin_x_ps);
+		tckmax_max_ps = max(tckmax_max_ps, dimm_params[i].tckmax_ps);
+		trcd_ps = max(trcd_ps, dimm_params[i].trcd_ps);
+		trp_ps = max(trp_ps, dimm_params[i].trp_ps);
+		tras_ps = max(tras_ps, dimm_params[i].tras_ps);
+		twr_ps = max(twr_ps, dimm_params[i].twr_ps);
+		twtr_ps = max(twtr_ps, dimm_params[i].twtr_ps);
+		trfc_ps = max(trfc_ps, dimm_params[i].trfc_ps);
+		trrd_ps = max(trrd_ps, dimm_params[i].trrd_ps);
+		trc_ps = max(trc_ps, dimm_params[i].trc_ps);
+		tis_ps = max(tis_ps, dimm_params[i].tis_ps);
+		tih_ps = max(tih_ps, dimm_params[i].tih_ps);
+		tds_ps = max(tds_ps, dimm_params[i].tds_ps);
+		tdh_ps = max(tdh_ps, dimm_params[i].tdh_ps);
+		trtp_ps = max(trtp_ps, dimm_params[i].trtp_ps);
+		tqhs_ps = max(tqhs_ps, dimm_params[i].tqhs_ps);
 		refresh_rate_ps = max(refresh_rate_ps,
 				      dimm_params[i].refresh_rate_ps);
 
 		/*
-		 * Find maximum tDQSQ_max_ps to find slowest.
+		 * Find maximum tdqsq_max_ps to find slowest.
 		 *
 		 * FIXME: is finding the slowest value the correct
 		 * strategy for this parameter?
 		 */
-		tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
+		tdqsq_max_ps = max(tdqsq_max_ps, dimm_params[i].tdqsq_max_ps);
 	}
 
 	outpdimm->ndimms_present = number_of_dimms - temp1;
@@ -183,25 +183,25 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 		return 0;
 	}
 
-	outpdimm->tCKmin_X_ps = tCKmin_X_ps;
-	outpdimm->tCKmax_ps = tCKmax_ps;
-	outpdimm->tCKmax_max_ps = tCKmax_max_ps;
-	outpdimm->tRCD_ps = tRCD_ps;
-	outpdimm->tRP_ps = tRP_ps;
-	outpdimm->tRAS_ps = tRAS_ps;
-	outpdimm->tWR_ps = tWR_ps;
-	outpdimm->tWTR_ps = tWTR_ps;
-	outpdimm->tRFC_ps = tRFC_ps;
-	outpdimm->tRRD_ps = tRRD_ps;
-	outpdimm->tRC_ps = tRC_ps;
+	outpdimm->tckmin_x_ps = tckmin_x_ps;
+	outpdimm->tckmax_ps = tckmax_ps;
+	outpdimm->tckmax_max_ps = tckmax_max_ps;
+	outpdimm->trcd_ps = trcd_ps;
+	outpdimm->trp_ps = trp_ps;
+	outpdimm->tras_ps = tras_ps;
+	outpdimm->twr_ps = twr_ps;
+	outpdimm->twtr_ps = twtr_ps;
+	outpdimm->trfc_ps = trfc_ps;
+	outpdimm->trrd_ps = trrd_ps;
+	outpdimm->trc_ps = trc_ps;
 	outpdimm->refresh_rate_ps = refresh_rate_ps;
-	outpdimm->tIS_ps = tIS_ps;
-	outpdimm->tIH_ps = tIH_ps;
-	outpdimm->tDS_ps = tDS_ps;
-	outpdimm->tDH_ps = tDH_ps;
-	outpdimm->tRTP_ps = tRTP_ps;
-	outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
-	outpdimm->tQHS_ps = tQHS_ps;
+	outpdimm->tis_ps = tis_ps;
+	outpdimm->tih_ps = tih_ps;
+	outpdimm->tds_ps = tds_ps;
+	outpdimm->tdh_ps = tdh_ps;
+	outpdimm->trtp_ps = trtp_ps;
+	outpdimm->tdqsq_max_ps = tdqsq_max_ps;
+	outpdimm->tqhs_ps = tqhs_ps;
 
 	/* Determine common burst length for all DIMMs. */
 	temp1 = 0xff;
@@ -210,7 +210,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 			temp1 &= dimm_params[i].burst_lengths_bitmask;
 		}
 	}
-	outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
+	outpdimm->all_dimms_burst_lengths_bitmask = temp1;
 
 	/* Determine if all DIMMs registered buffered. */
 	temp1 = temp2 = 0;
@@ -232,19 +232,19 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 		}
 	}
 
-	outpdimm->all_DIMMs_registered = 0;
-	outpdimm->all_DIMMs_unbuffered = 0;
+	outpdimm->all_dimms_registered = 0;
+	outpdimm->all_dimms_unbuffered = 0;
 	if (temp1 && !temp2) {
-		outpdimm->all_DIMMs_registered = 1;
+		outpdimm->all_dimms_registered = 1;
 	} else if (!temp1 && temp2) {
-		outpdimm->all_DIMMs_unbuffered = 1;
+		outpdimm->all_dimms_unbuffered = 1;
 	} else {
 		printf("ERROR:  Mix of registered buffered and unbuffered "
 				"DIMMs detected!\n");
 	}
 
 	temp1 = 0;
-	if (outpdimm->all_DIMMs_registered)
+	if (outpdimm->all_dimms_registered)
 		for (j = 0; j < 16; j++) {
 			outpdimm->rcw[j] = dimm_params[0].rcw[j];
 			for (i = 1; i < number_of_dimms; i++) {
@@ -279,13 +279,13 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	for (i = 0; i < number_of_dimms; i++) {
 		if (dimm_params[i].n_ranks) {
 			temp2 = 0;
-			temp2 |= 1 << dimm_params[i].caslat_X;
-			temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
-			temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
+			temp2 |= 1 << dimm_params[i].caslat_x;
+			temp2 |= 1 << dimm_params[i].caslat_x_minus_1;
+			temp2 |= 1 << dimm_params[i].caslat_x_minus_2;
 			/*
 			 * FIXME: If there was no entry for X-2 (X-1) in
-			 * the SPD, then caslat_X_minus_2
-			 * (caslat_X_minus_1) contains either 255 or
+			 * the SPD, then caslat_x_minus_2
+			 * (caslat_x_minus_1) contains either 255 or
 			 * 0xFFFFFFFF because that's what the glorious
 			 * __ilog2 function returns for an input of 0.
 			 * On 32-bit PowerPC, left shift counts with bit
@@ -313,42 +313,42 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 			if (!dimm_params[i].n_ranks) {
 				continue;
 			}
-			if (dimm_params[i].caslat_X == temp2) {
-				if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
+			if (dimm_params[i].caslat_x == temp2) {
+				if (mclk_ps >= dimm_params[i].tckmin_x_ps) {
 					debug("CL = %u ok on DIMM %u at tCK=%u"
 					    " ps with its tCKmin_X_ps of %u\n",
 					       temp2, i, mclk_ps,
-					       dimm_params[i].tCKmin_X_ps);
+					       dimm_params[i].tckmin_x_ps);
 					continue;
 				} else {
 					not_ok++;
 				}
 			}
 
-			if (dimm_params[i].caslat_X_minus_1 == temp2) {
-				unsigned int tCKmin_X_minus_1_ps
-					= dimm_params[i].tCKmin_X_minus_1_ps;
-				if (mclk_ps >= tCKmin_X_minus_1_ps) {
+			if (dimm_params[i].caslat_x_minus_1 == temp2) {
+				unsigned int tckmin_x_minus_1_ps
+					= dimm_params[i].tckmin_x_minus_1_ps;
+				if (mclk_ps >= tckmin_x_minus_1_ps) {
 					debug("CL = %u ok on DIMM %u at "
 						"tCK=%u ps with its "
-						"tCKmin_X_minus_1_ps of %u\n",
+						"tckmin_x_minus_1_ps of %u\n",
 					       temp2, i, mclk_ps,
-					       tCKmin_X_minus_1_ps);
+					       tckmin_x_minus_1_ps);
 					continue;
 				} else {
 					not_ok++;
 				}
 			}
 
-			if (dimm_params[i].caslat_X_minus_2 == temp2) {
-				unsigned int tCKmin_X_minus_2_ps
-					= dimm_params[i].tCKmin_X_minus_2_ps;
-				if (mclk_ps >= tCKmin_X_minus_2_ps) {
+			if (dimm_params[i].caslat_x_minus_2 == temp2) {
+				unsigned int tckmin_x_minus_2_ps
+					= dimm_params[i].tckmin_x_minus_2_ps;
+				if (mclk_ps >= tckmin_x_minus_2_ps) {
 					debug("CL = %u ok on DIMM %u at "
 						"tCK=%u ps with its "
-						"tCKmin_X_minus_2_ps of %u\n",
+						"tckmin_x_minus_2_ps of %u\n",
 					       temp2, i, mclk_ps,
-					       tCKmin_X_minus_2_ps);
+					       tckmin_x_minus_2_ps);
 					continue;
 				} else {
 					not_ok++;
@@ -397,11 +397,11 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	} else {
 		debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
 	}
-	outpdimm->all_DIMMs_ECC_capable = temp1;
+	outpdimm->all_dimms_ecc_capable = temp1;
 
 #ifndef CONFIG_FSL_DDR3
 	/* FIXME: move to somewhere else to validate. */
-	if (mclk_ps > tCKmax_max_ps) {
+	if (mclk_ps > tckmax_max_ps) {
 		printf("Warning: some of the installed DIMMs "
 				"can not operate this slowly.\n");
 		return 1;
@@ -464,10 +464,10 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 
 #if defined(CONFIG_FSL_DDR2)
 	if (lowest_good_caslat < 4) {
-		additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
-			? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
-		if (mclk_to_picos(additive_latency) > tRCD_ps) {
-			additive_latency = picos_to_mclk(tRCD_ps);
+		additive_latency = (picos_to_mclk(trcd_ps) > lowest_good_caslat)
+			? picos_to_mclk(trcd_ps) - lowest_good_caslat : 0;
+		if (mclk_to_picos(additive_latency) > trcd_ps) {
+			additive_latency = picos_to_mclk(trcd_ps);
 			debug("setting additive_latency to %u because it was "
 				" greater than tRCD_ps\n", additive_latency);
 		}
@@ -487,7 +487,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	 *
 	 * AL <= tRCD(min)
 	 */
-	if (mclk_to_picos(additive_latency) > tRCD_ps) {
+	if (mclk_to_picos(additive_latency) > trcd_ps) {
 		printf("Error: invalid additive latency exceeds tRCD(min).\n");
 		return 1;
 	}
@@ -507,15 +507,15 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	 */
 	outpdimm->additive_latency = additive_latency;
 
-	debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps);
-	debug("tRCD_ps   = %u\n", outpdimm->tRCD_ps);
-	debug("tRP_ps    = %u\n", outpdimm->tRP_ps);
-	debug("tRAS_ps   = %u\n", outpdimm->tRAS_ps);
-	debug("tWR_ps    = %u\n", outpdimm->tWR_ps);
-	debug("tWTR_ps   = %u\n", outpdimm->tWTR_ps);
-	debug("tRFC_ps   = %u\n", outpdimm->tRFC_ps);
-	debug("tRRD_ps   = %u\n", outpdimm->tRRD_ps);
-	debug("tRC_ps    = %u\n", outpdimm->tRC_ps);
+	debug("tCKmin_ps = %u\n", outpdimm->tckmin_x_ps);
+	debug("trcd_ps   = %u\n", outpdimm->trcd_ps);
+	debug("trp_ps    = %u\n", outpdimm->trp_ps);
+	debug("tras_ps   = %u\n", outpdimm->tras_ps);
+	debug("twr_ps    = %u\n", outpdimm->twr_ps);
+	debug("twtr_ps   = %u\n", outpdimm->twtr_ps);
+	debug("trfc_ps   = %u\n", outpdimm->trfc_ps);
+	debug("trrd_ps   = %u\n", outpdimm->trrd_ps);
+	debug("trc_ps    = %u\n", outpdimm->trc_ps);
 
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 842bf1989e..b9ae9509be 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -457,7 +457,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 			 * which is currently STEP_ASSIGN_ADDRESSES.
 			 */
 			populate_memctl_options(
-					timing_params[i].all_DIMMs_registered,
+					timing_params[i].all_dimms_registered,
 					&pinfo->memctl_opts[i],
 					pinfo->dimm_params[i], i);
 			/*
@@ -466,7 +466,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 			 * using fixed parameters, this function should be
 			 * be called from board init file.
 			 */
-			if (timing_params[i].all_DIMMs_registered)
+			if (timing_params[i].all_dimms_registered)
 				assert_reset = 1;
 		}
 		if (assert_reset) {
@@ -589,7 +589,7 @@ phys_size_t fsl_ddr_sdram(void)
 	 */
 	deassert_reset = board_need_mem_reset();
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
-		if (info.common_timing_params[i].all_DIMMs_registered)
+		if (info.common_timing_params[i].all_dimms_registered)
 			deassert_reset = 1;
 	}
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 30cdca497e..1297845553 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -499,7 +499,7 @@ static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
 	return 0;
 }
 
-unsigned int populate_memctl_options(int all_DIMMs_registered,
+unsigned int populate_memctl_options(int all_dimms_registered,
 			memctl_options_t *popts,
 			dimm_params_t *pdimm,
 			unsigned int ctrl_num)
@@ -635,20 +635,20 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	popts->ba_intlv_ctl = 0;
 
 	/* Memory Organization Parameters */
-	popts->registered_dimm_en = all_DIMMs_registered;
+	popts->registered_dimm_en = all_dimms_registered;
 
 	/* Operational Mode Paramters */
 
 	/* Pick ECC modes */
-	popts->ECC_mode = 0;		  /* 0 = disabled, 1 = enabled */
+	popts->ecc_mode = 0;		  /* 0 = disabled, 1 = enabled */
 #ifdef CONFIG_DDR_ECC
 	if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
 		if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
-			popts->ECC_mode = 1;
+			popts->ecc_mode = 1;
 	} else
-		popts->ECC_mode = 1;
+		popts->ecc_mode = 1;
 #endif
-	popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
+	popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
 
 	/*
 	 * Choose DQS config
@@ -656,9 +656,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 * 1 for DDR2
 	 */
 #if defined(CONFIG_FSL_DDR1)
-	popts->DQS_config = 0;
+	popts->dqs_config = 0;
 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
-	popts->DQS_config = 1;
+	popts->dqs_config = 1;
 #endif
 
 	/* Choose self-refresh during sleep. */
@@ -705,15 +705,15 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	/* Choose burst length. */
 #if defined(CONFIG_FSL_DDR3)
 #if defined(CONFIG_E500MC)
-	popts->OTF_burst_chop_en = 0;	/* on-the-fly burst chop disable */
+	popts->otf_burst_chop_en = 0;	/* on-the-fly burst chop disable */
 	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
 #else
 	if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
 		/* 32-bit or 16-bit bus */
-		popts->OTF_burst_chop_en = 0;
+		popts->otf_burst_chop_en = 0;
 		popts->burst_length = DDR_BL8;
 	} else {
-		popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
+		popts->otf_burst_chop_en = 1;	/* on-the-fly burst chop */
 		popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
 	}
 #endif
@@ -756,8 +756,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 *	- number of components, number of active ranks
 	 *	- how much time you want to spend playing around
 	 */
-	popts->twoT_en = 0;
-	popts->threeT_en = 0;
+	popts->twot_en = 0;
+	popts->threet_en = 0;
 
 	/* for RDIMM, address parity enable */
 	popts->ap_en = 1;
@@ -775,7 +775,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	popts->bstopre = 0x100;
 
 	/* Minimum CKE pulse width -- tCKE(MIN) */
-	popts->tCKE_clock_pulse_width_ps
+	popts->tcke_clock_pulse_width_ps
 		= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 
 	/*
@@ -786,17 +786,17 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 * FIXME: width, was considering looking at pdimm->primary_sdram_width
 	 */
 #if defined(CONFIG_FSL_DDR1)
-	popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
+	popts->tfaw_window_four_activates_ps = mclk_to_picos(1);
 
 #elif defined(CONFIG_FSL_DDR2)
 	/*
 	 * x4/x8;  some datasheets have 35000
 	 * x16 wide columns only?  Use 50000?
 	 */
-	popts->tFAW_window_four_activates_ps = 37500;
+	popts->tfaw_window_four_activates_ps = 37500;
 
 #elif defined(CONFIG_FSL_DDR3)
-	popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
+	popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
 #endif
 	popts->zq_en = 0;
 	popts->wrlvl_en = 0;
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
index bd312ad5c5..2cad6e2857 100644
--- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
+++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h
@@ -45,48 +45,48 @@ typedef struct dimm_params_s {
 
 	unsigned int mtb_ps;	/* medium timebase ps, only for ddr3 */
 	unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
-	unsigned int tAA_ps;	/* minimum CAS latency time, only for ddr3 */
-	unsigned int tFAW_ps;	/* four active window delay, only for ddr3 */
+	unsigned int taa_ps;	/* minimum CAS latency time, only for ddr3 */
+	unsigned int tfaw_ps;	/* four active window delay, only for ddr3 */
 
 	/*
 	 * SDRAM clock periods
 	 * The range for these are 1000-10000 so a short should be sufficient
 	 */
-	unsigned int tCKmin_X_ps;
-	unsigned int tCKmin_X_minus_1_ps;
-	unsigned int tCKmin_X_minus_2_ps;
-	unsigned int tCKmax_ps;
+	unsigned int tckmin_x_ps;
+	unsigned int tckmin_x_minus_1_ps;
+	unsigned int tckmin_x_minus_2_ps;
+	unsigned int tckmax_ps;
 
 	/* SPD-defined CAS latencies */
-	unsigned int caslat_X;
-	unsigned int caslat_X_minus_1;
-	unsigned int caslat_X_minus_2;
+	unsigned int caslat_x;
+	unsigned int caslat_x_minus_1;
+	unsigned int caslat_x_minus_2;
 
 	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
 
 	/* basic timing parameters */
-	unsigned int tRCD_ps;
-	unsigned int tRP_ps;
-	unsigned int tRAS_ps;
+	unsigned int trcd_ps;
+	unsigned int trp_ps;
+	unsigned int tras_ps;
 
-	unsigned int tWR_ps;	/* maximum = 63750 ps */
-	unsigned int tWTR_ps;	/* maximum = 63750 ps */
-	unsigned int tRFC_ps;   /* max = 255 ns + 256 ns + .75 ns
+	unsigned int twr_ps;	/* maximum = 63750 ps */
+	unsigned int twtr_ps;	/* maximum = 63750 ps */
+	unsigned int trfc_ps;   /* max = 255 ns + 256 ns + .75 ns
 				       = 511750 ps */
 
-	unsigned int tRRD_ps;	/* maximum = 63750 ps */
-	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
+	unsigned int trrd_ps;	/* maximum = 63750 ps */
+	unsigned int trc_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
 
 	unsigned int refresh_rate_ps;
 
 	/* DDR3 doesn't need these as below */
-	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
-	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
-	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
-	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
-	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
-	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
-	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
+	unsigned int tis_ps;	/* byte 32, spd->ca_setup */
+	unsigned int tih_ps;	/* byte 33, spd->ca_hold */
+	unsigned int tds_ps;	/* byte 34, spd->data_setup */
+	unsigned int tdh_ps;	/* byte 35, spd->data_hold */
+	unsigned int trtp_ps;	/* byte 38, spd->trtp */
+	unsigned int tdqsq_max_ps;	/* byte 44, spd->tdqsq */
+	unsigned int tqhs_ps;	/* byte 45, spd->tqhs */
 
 	/* DDR3 RDIMM */
 	unsigned char rcw[16];	/* Register Control Word 0-15 */
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index f4eec82d5d..2c3c514ba3 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -219,13 +219,13 @@ typedef struct fsl_ddr_cfg_regs_s {
 } fsl_ddr_cfg_regs_t;
 
 typedef struct memctl_options_partial_s {
-	unsigned int all_DIMMs_ECC_capable;
-	unsigned int all_DIMMs_tCKmax_ps;
-	unsigned int all_DIMMs_burst_lengths_bitmask;
-	unsigned int all_DIMMs_registered;
-	unsigned int all_DIMMs_unbuffered;
+	unsigned int all_dimms_ecc_capable;
+	unsigned int all_dimms_tckmax_ps;
+	unsigned int all_dimms_burst_lengths_bitmask;
+	unsigned int all_dimms_registered;
+	unsigned int all_dimms_unbuffered;
 	/*	unsigned int lowest_common_SPD_caslat; */
-	unsigned int all_DIMMs_minimum_tRCD_ps;
+	unsigned int all_dimms_minimum_trcd_ps;
 } memctl_options_partial_t;
 
 #define DDR_DATA_BUS_WIDTH_64 0
@@ -261,10 +261,10 @@ typedef struct memctl_options_s {
 	unsigned int addr_hash;
 
 	/* Operational mode parameters */
-	unsigned int ECC_mode;	 /* Use ECC? */
+	unsigned int ecc_mode;	 /* Use ECC? */
 	/* Initialize ECC using memory controller? */
-	unsigned int ECC_init_using_memctl;
-	unsigned int DQS_config;	/* Use DQS? maybe only with DDR2? */
+	unsigned int ecc_init_using_memctl;
+	unsigned int dqs_config;	/* Use DQS? maybe only with DDR2? */
 	/* SREN - self-refresh during sleep */
 	unsigned int self_refresh_in_sleep;
 	unsigned int dynamic_power;	/* DYN_PWR */
@@ -272,7 +272,7 @@ typedef struct memctl_options_s {
 	unsigned int data_bus_width;
 	unsigned int burst_length;	/* BL4, OTF and BL8 */
 	/* On-The-Fly Burst Chop enable */
-	unsigned int OTF_burst_chop_en;
+	unsigned int otf_burst_chop_en;
 	/* mirrior DIMMs for DDR3 */
 	unsigned int mirrored_dimm;
 	unsigned int quad_rank_present;
@@ -297,11 +297,11 @@ typedef struct memctl_options_s {
 	unsigned int wrlvl_ctl_3;
 
 	unsigned int half_strength_driver_enable;
-	unsigned int twoT_en;
-	unsigned int threeT_en;
+	unsigned int twot_en;
+	unsigned int threet_en;
 	unsigned int bstopre;
-	unsigned int tCKE_clock_pulse_width_ps;	/* tCKE */
-	unsigned int tFAW_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
+	unsigned int tcke_clock_pulse_width_ps;	/* tCKE */
+	unsigned int tfaw_window_four_activates_ps;	/* tFAW --  FOUR_ACT */
 
 	/* Rtt impedance */
 	unsigned int rtt_override;		/* rtt_override enable */
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
index 01c9efff97..814a53577e 100644
--- a/arch/powerpc/include/asm/immap_512x.h
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -279,8 +279,8 @@ typedef struct ddr512x {
 	u32 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
 	u32 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
 	u32 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
-	u32 DQS_config_offset_count;	/* DQS Config Offset Count */
-	u32 DQS_config_offset_time;	/* DQS Config Offset Time */
+	u32 dqs_config_offset_count;	/* DQS Config Offset Count */
+	u32 dqs_config_offset_time;	/* DQS Config Offset Time */
 	u32 DQS_delay_status;	/* DQS Delay Status */
 	u32 res0[0xF];
 	u32 prioman_config1;	/* Priority Manager Configuration */