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| author | York Sun <yorksun@freescale.com> | 2013-03-25 07:30:11 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-02 16:57:33 -0500 |
| commit | e22be77a4a61e0deb85f95ae48f26841000c65cb (patch) | |
| tree | 404c39afa6dca631c9fd8499b9c706548a266ee0 /arch/powerpc/include | |
| parent | 06c11796377c488c95122c671d0665cbba6985c0 (diff) | |
| download | talos-obmc-uboot-e22be77a4a61e0deb85f95ae48f26841000c65cb.tar.gz talos-obmc-uboot-e22be77a4a61e0deb85f95ae48f26841000c65cb.zip | |
powerpc/mpc85xx: Extend workaround for erratum DDR_A003 to other SoCs
Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index db16af957e..7267611cbc 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -335,6 +335,7 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 @@ -368,6 +369,7 @@ #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 #define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 @@ -445,6 +447,7 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_USB14 +#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 |
