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| author | Shengzhou Liu <Shengzhou.Liu@freescale.com> | 2015-10-26 13:51:58 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-11-02 08:51:50 -0800 |
| commit | 96d59e9d6aa74e35c63dc74da10e41f8ba0f6de4 (patch) | |
| tree | 8c31900002b4c0751d61b944ca7b1711c85dd149 /arch/powerpc/cpu | |
| parent | 94af6842df93dc0b5aa092e3221d35950cacf2d0 (diff) | |
| download | talos-obmc-uboot-96d59e9d6aa74e35c63dc74da10e41f8ba0f6de4.tar.gz talos-obmc-uboot-96d59e9d6aa74e35c63dc74da10e41f8ba0f6de4.zip | |
mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1
T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing
for PLL ratio.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/speed.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index d954fe2fd2..e732969e41 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -131,7 +131,8 @@ void get_sys_info(sys_info_t *sys_info) * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) + defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \ + defined(CONFIG_PPC_T2081) svr = get_svr(); switch (SVR_SOC_VER(svr)) { case SVR_T4240: |
