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| author | York Sun <yorksun@freescale.com> | 2012-08-17 08:22:39 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-08-23 12:16:55 -0500 |
| commit | a4c66509f1b95884e5753d5a30cf2cf884adb821 (patch) | |
| tree | 0e6a44b7d2b286afc7bafff558277d51ca182195 /arch/powerpc/cpu/mpc85xx/cpu.c | |
| parent | fcea30688fd8c47d54473ffd0f551a5e6efc74a0 (diff) | |
| download | talos-obmc-uboot-a4c66509f1b95884e5753d5a30cf2cf884adb821.tar.gz talos-obmc-uboot-a4c66509f1b95884e5753d5a30cf2cf884adb821.zip | |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/cpu.c')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cpu.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 8d2ef9ffc7..5ddb29435c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -430,11 +430,21 @@ static void dump_spd_ddr_reg(void) case 0: ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR; break; -#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR +#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR; break; #endif +#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR; + break; +#endif default: printf("%s unexpected controller number = %u\n", __func__, i); |
