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| author | Thomas Chou <thomas@wytron.com.tw> | 2014-08-25 17:09:07 +0800 |
|---|---|---|
| committer | Thomas Chou <thomas@wytron.com.tw> | 2014-08-30 17:48:43 +0800 |
| commit | 57cfeb5140642b1071b01a7cc5c34d4ef3166180 (patch) | |
| tree | 4947572a662637ff402427d106d57144f29e5988 /arch/nios2 | |
| parent | 8645071006a0b577ae4660f4a271f42c081ef4ab (diff) | |
| download | talos-obmc-uboot-57cfeb5140642b1071b01a7cc5c34d4ef3166180.tar.gz talos-obmc-uboot-57cfeb5140642b1071b01a7cc5c34d4ef3166180.zip | |
nios2: move nios2.h to arch asm directory
The nios2.h is nios2 cpu specific, and should go arch asm
directory.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Diffstat (limited to 'arch/nios2')
| -rw-r--r-- | arch/nios2/cpu/cpu.c | 2 | ||||
| -rw-r--r-- | arch/nios2/cpu/interrupts.c | 2 | ||||
| -rw-r--r-- | arch/nios2/include/asm/nios2.h | 40 |
3 files changed, 42 insertions, 2 deletions
diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 36ea90bc8c..39ae97221c 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -6,7 +6,7 @@ */ #include <common.h> -#include <nios2.h> +#include <asm/nios2.h> #include <asm/cache.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/nios2/cpu/interrupts.c b/arch/nios2/cpu/interrupts.c index b363a1feb0..9d7e193e28 100644 --- a/arch/nios2/cpu/interrupts.c +++ b/arch/nios2/cpu/interrupts.c @@ -9,7 +9,7 @@ */ -#include <nios2.h> +#include <asm/nios2.h> #include <asm/types.h> #include <asm/io.h> #include <asm/ptrace.h> diff --git a/arch/nios2/include/asm/nios2.h b/arch/nios2/include/asm/nios2.h new file mode 100644 index 0000000000..abe4df3581 --- /dev/null +++ b/arch/nios2/include/asm/nios2.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_NIOS2_H__ +#define __ASM_NIOS2_H__ + +/*------------------------------------------------------------------------ + * Control registers -- use with wrctl() & rdctl() + *----------------------------------------------------------------------*/ +#define CTL_STATUS 0 /* Processor status reg */ +#define CTL_ESTATUS 1 /* Exception status reg */ +#define CTL_BSTATUS 2 /* Break status reg */ +#define CTL_IENABLE 3 /* Interrut enable reg */ +#define CTL_IPENDING 4 /* Interrut pending reg */ + +/*------------------------------------------------------------------------ + * Access to control regs + *----------------------------------------------------------------------*/ + +#define rdctl(reg) __builtin_rdctl(reg) +#define wrctl(reg, val) __builtin_wrctl(reg, val) + +/*------------------------------------------------------------------------ + * Control reg bit masks + *----------------------------------------------------------------------*/ +#define STATUS_IE (1<<0) /* Interrupt enable */ +#define STATUS_U (1<<1) /* User-mode */ + +/*------------------------------------------------------------------------ + * Bit-31 Cache bypass -- only valid for data access. When data cache + * is not implemented, bit 31 is ignored for compatibility. + *----------------------------------------------------------------------*/ +#define CACHE_BYPASS(a) ((a) | 0x80000000) +#define CACHE_NO_BYPASS(a) ((a) & ~0x80000000) + +#endif /* __ASM_NIOS2_H__ */ |
