ARM: uniphier: refactor SBC init code

There is a bunch of duplication in the System Bus Controller init
code.  Roughly, there are two types in the SBC mode:  Adress/Data
Multiplex Mode and Save Pins Mode.  Consolidate per-SoC functions
into the two, plus per-SoC optional init code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 1 insertions, 33 deletions

diff --git a/arch/arm/mach-uniphier/sbc/sbc-sld3.c b/arch/arm/mach-uniphier/sbc/sbc-sld3.c
index c03c2843a6..ac9d0301be 100644
--- a/arch/arm/mach-uniphier/sbc/sbc-sld3.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-sld3.c
@@ -4,45 +4,13 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <common.h>
 #include <linux/io.h>
 
 #include "../init.h"
 #include "../sg-regs.h"
-#include "sbc-regs.h"
 
-int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
+int uniphier_sld3_sbc_init(const struct uniphier_board_data *bd)
 {
-	/* only address/data multiplex mode is supported */
-
-	/*
-	 * Only CS1 is connected to support card.
-	 * BKSZ[1:0] should be set to "01".
-	 */
-	writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
-	writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
-	writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
-
-	if (boot_is_swapped()) {
-		/*
-		 * Boot Swap On: boot from external NOR/SRAM
-		 * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
-		 *
-		 * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
-		 * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
-		 */
-		writel(0x0000bc01, SBBASE0);
-	} else {
-		/*
-		 * Boot Swap Off: boot from mask ROM
-		 * 0x40000000-0x41ffffff: mask ROM
-		 * 0x42000000-0x43efffff: memory bank (31MB)
-		 * 0x43f00000-0x43ffffff: peripherals (1MB)
-		 */
-		writel(0x0000be01, SBBASE0); /* dummy */
-		writel(0x0200be01, SBBASE1);
-	}
-
 	sg_set_pinsel(99, 1, 4, 4);	/* GPIO26 -> EA24 */
 
 	return 0;