ARM: uniphier: allow to enable multiple SoCs

Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 49 insertions, 0 deletions

diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
new file mode 100644
index 0000000000..160d3ef299
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_ld4_pin_init(void)
+{
+	u32 tmp;
+
+	/* Comment format:    PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+	sg_set_pinsel(158, 0, 8, 4);	/* XNFRE -> XNFRE_GB */
+	sg_set_pinsel(159, 0, 8, 4);	/* XNFWE -> XNFWE_GB */
+	sg_set_pinsel(160, 0, 8, 4);	/* XFALE -> NFALE_GB */
+	sg_set_pinsel(161, 0, 8, 4);	/* XFCLE -> NFCLE_GB */
+	sg_set_pinsel(162, 0, 8, 4);	/* XNFWP -> XFNWP_GB */
+	sg_set_pinsel(163, 0, 8, 4);	/* XNFCE0 -> XNFCE0_GB */
+	sg_set_pinsel(164, 0, 8, 4);	/* NANDRYBY0 -> NANDRYBY0_GB */
+	sg_set_pinsel(22, 0, 8, 4);	/* MMCCLK  -> XFNCE1_GB */
+	sg_set_pinsel(23, 0, 8, 4);	/* MMCCMD  -> NANDRYBY1_GB */
+	sg_set_pinsel(24, 0, 8, 4);	/* MMCDAT0 -> NFD0_GB */
+	sg_set_pinsel(25, 0, 8, 4);	/* MMCDAT1 -> NFD1_GB */
+	sg_set_pinsel(26, 0, 8, 4);	/* MMCDAT2 -> NFD2_GB */
+	sg_set_pinsel(27, 0, 8, 4);	/* MMCDAT3 -> NFD3_GB */
+	sg_set_pinsel(28, 0, 8, 4);	/* MMCDAT4 -> NFD4_GB */
+	sg_set_pinsel(29, 0, 8, 4);	/* MMCDAT5 -> NFD5_GB */
+	sg_set_pinsel(30, 0, 8, 4);	/* MMCDAT6 -> NFD6_GB */
+	sg_set_pinsel(31, 0, 8, 4);	/* MMCDAT7 -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+	sg_set_pinsel(53, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
+	sg_set_pinsel(54, 0, 8, 4);	/* USB0OD   -> USB0OD */
+	sg_set_pinsel(55, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
+	sg_set_pinsel(56, 0, 8, 4);	/* USB1OD   -> USB1OD */
+	/* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */
+	/* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */
+#endif
+
+	tmp = readl(SG_IECTRL);
+	tmp |= 0x41;
+	writel(tmp, SG_IECTRL);
+}