ARM: uniphier: drop UniPhier specific SMP code

The latest Linux can directly handle SMP operations for UniPhier SoCs
without any help of U-boot.  Drop the relevant code from U-boot.

See commit b1e4006aeda8c8784029de17d47987c21ea75f6d ("ARM: uniphier:
rework SMP operations to use trampoline code") in Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

1 files changed, 0 insertions, 53 deletions

diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index 66cad42dde..5936045e86 100644
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -44,59 +44,6 @@ ENTRY(lowlevel_init)
 
 	bl	enable_mmu
 
-#ifdef CONFIG_UNIPHIER_SMP
-secondary_startup:
-	/*
-	 * Entry point for secondary CPUs
-	 *
-	 * The Boot ROM has already enabled MMU for the secondary CPUs as well
-	 * as for the primary one.  The MMU table embedded in the Boot ROM
-	 * prohibits the DRAM access, so it is impossible to bring the
-	 * secondary CPUs into DRAM directly.  They must jump here into SPL,
-	 * which is run on L2 cache.
-	 *
-	 * Boot Sequence
-	 *  [primary CPU]                    [secondary CPUs]
-	 *  start from Boot ROM             start from Boot ROM
-	 *     jump to SPL                    sleep in Boot ROM
-	 *  kick secondaries   ---(sev)--->    jump to SPL
-	 *  jump to U-Boot main               sleep in SPL
-	 *  jump to Linux
-	 *  kick secondaries   ---(sev)--->    jump to Linux
-	 */
-
-	/* branch by CPU ID */
-	mrc	p15, 0, r0, c0, c0, 5	@ MPIDR (Multiprocessor Affinity Register)
-	and  	r0, r0, #0x3
-	cmp	r0, #0x0
-	beq	primary_cpu
-	/* only for secondary CPUs */
-	ldr	r1, =ROM_BOOT_ROMRSV2	@ The last data access to L2 cache
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
-	orr	r0, r0, #CR_I		@ Enable ICache
-	bic	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache must be disabled
-	mcr	p15, 0, r0, c1, c0, 0	@ before jumping to Linux
-	mov	r0, #0
-	str	r0, [r1]
-	b	1f
-	/*
-	 * L2 cache is shared among all the CPUs and it might be disabled by
-	 * the primary one.  Before that, the following 5 lines must be cached
-	 * on the Icaches of the secondary CPUs.
-	 */
-0:	wfe				@ kicked by Linux
-1:	ldr	r0, [r1]
-	cmp	r0, #0
-	bxne	r0			@ r0: Linux entry for secondary CPUs
-	b	0b
-primary_cpu:
-	ldr	r1, =ROM_BOOT_ROMRSV2
-	ldr	r0, =secondary_startup
-	str	r0, [r1]
-	ldr	r0, [r1]		@ make sure str is complete before sev
-	sev				@ kick the secondary CPU
-#endif
-
 	bl	setup_init_ram		@ RAM area for temporary stack pointer
 
 	mov	lr, r8			@ restore link