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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-07-21 14:04:22 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-07-23 23:42:22 +0900 |
| commit | 3365b4eb5543ae26579321da34cca42e38ac130f (patch) | |
| tree | 3da8e615f2f020eda20f50cef1b79b83c36e4bd3 /arch/arm/mach-uniphier/include | |
| parent | ad6670ee12a1783aeb54881fa5bb2e5582ba2dbc (diff) | |
| download | talos-obmc-uboot-3365b4eb5543ae26579321da34cca42e38ac130f.tar.gz talos-obmc-uboot-3365b4eb5543ae26579321da34cca42e38ac130f.zip | |
ARM: UniPhier: add PH1-sLD3 SoC support
The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/include')
| -rw-r--r-- | arch/arm/mach-uniphier/include/mach/sc-regs.h | 6 | ||||
| -rw-r--r-- | arch/arm/mach-uniphier/include/mach/sg-regs.h | 5 |
2 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h index 20878e2d1c..df50294077 100644 --- a/arch/arm/mach-uniphier/include/mach/sc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h @@ -1,7 +1,7 @@ /* * UniPhier SC (System Control) block registers * - * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,7 +9,11 @@ #ifndef ARCH_SC_REGS_H #define ARCH_SC_REGS_H +#if defined(CONFIG_MACH_PH1_SLD3) +#define SC_BASE_ADDR 0xf1840000 +#else #define SC_BASE_ADDR 0x61840000 +#endif #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) #define SC_DPLLCTRL_SSC_EN (0x1 << 31) diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h index a65f058ee2..43a6c35339 100644 --- a/arch/arm/mach-uniphier/include/mach/sg-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h @@ -55,11 +55,12 @@ #if defined(CONFIG_MACH_PH1_PRO4) # define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8) -#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#elif defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \ + defined(CONFIG_MACH_PH1_SLD8) # define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4) #endif -#if defined(CONFIG_MACH_PH1_PRO4) +#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_PRO4) #define SG_PINSELBITS 4 #elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) #define SG_PINSELBITS 8 |
