ARM: uniphier: allow to enable multiple SoCs

Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

5 files changed, 161 insertions, 6 deletions

diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/include/mach/boot-device.h
index 7a10f1c5b2..eddb25ffa4 100644
--- a/arch/arm/mach-uniphier/include/mach/boot-device.h
+++ b/arch/arm/mach-uniphier/include/mach/boot-device.h
@@ -1,6 +1,5 @@
 /*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -8,13 +7,15 @@
 #ifndef _ASM_BOOT_DEVICE_H_
 #define _ASM_BOOT_DEVICE_H_
 
-int get_boot_mode_sel(void);
-
 struct boot_device_info {
 	u32 type;
 	char *info;
 };
 
-extern struct boot_device_info boot_device_table[];
+u32 ph1_sld3_boot_device(void);
+u32 ph1_ld4_boot_device(void);
+
+void ph1_sld3_boot_mode_show(void);
+void ph1_ld4_boot_mode_show(void);
 
 #endif /* _ASM_BOOT_DEVICE_H_ */
diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
index 01f5c52c9c..adcc972877 100644
--- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
@@ -168,7 +168,9 @@ struct ddrphy {
 #define DDRPHY_BASE(ch, phy)	(0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
 
 #ifndef __ASSEMBLY__
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
 void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
 int ddrphy_training(struct ddrphy __iomem *phy);
 #endif
diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/include/mach/init.h
new file mode 100644
index 0000000000..228cbb1a19
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/init.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MACH_INIT_H
+#define __MACH_INIT_H
+
+struct uniphier_board_data {
+	unsigned long dram_ch0_base;
+	unsigned long dram_ch0_size;
+	unsigned long dram_ch0_width;
+	unsigned long dram_ch1_base;
+	unsigned long dram_ch1_size;
+	unsigned long dram_ch1_width;
+	unsigned long dram_ch2_base;
+	unsigned long dram_ch2_size;
+	unsigned long dram_ch2_width;
+	unsigned int  dram_freq;
+};
+
+const struct uniphier_board_data *uniphier_get_board_param(const void *fdt);
+
+int ph1_sld3_init(const struct uniphier_board_data *bd);
+int ph1_ld4_init(const struct uniphier_board_data *bd);
+int ph1_pro4_init(const struct uniphier_board_data *bd);
+int ph1_sld8_init(const struct uniphier_board_data *bd);
+
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
+int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
+int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
+#else
+static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
+{
+	return 0;
+}
+
+static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
+{
+	return 0;
+}
+
+static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
+{
+	return 0;
+}
+#endif
+
+int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
+int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
+
+int memconf_init(const struct uniphier_board_data *bd);
+int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
+int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
+int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
+int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
+int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
+
+int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
+
+int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
+int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
+
+void ph1_sld3_pin_init(void);
+void ph1_ld4_pin_init(void);
+void ph1_pro4_pin_init(void);
+void ph1_sld8_pin_init(void);
+
+void ph1_ld4_clk_init(void);
+void ph1_pro4_clk_init(void);
+
+#define pr_err(fmt, args...)	printf(fmt, ##args)
+
+#endif /* __MACH_INIT_H */
diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h
index c886e1c655..d8239f28bc 100644
--- a/arch/arm/mach-uniphier/include/mach/sg-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h
@@ -25,26 +25,32 @@
 /* Memory Configuration */
 #define SG_MEMCONF			(SG_CTRL_BASE | 0x0400)
 
+#define SG_MEMCONF_CH0_SZ_MASK		((0x1 << 10) | (0x03 << 0))
 #define SG_MEMCONF_CH0_SZ_64M		((0x0 << 10) | (0x01 << 0))
 #define SG_MEMCONF_CH0_SZ_128M		((0x0 << 10) | (0x02 << 0))
 #define SG_MEMCONF_CH0_SZ_256M		((0x0 << 10) | (0x03 << 0))
 #define SG_MEMCONF_CH0_SZ_512M		((0x1 << 10) | (0x00 << 0))
 #define SG_MEMCONF_CH0_SZ_1G		((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_MASK		(0x1 << 8)
 #define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
 #define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)
 
+#define SG_MEMCONF_CH1_SZ_MASK		((0x1 << 11) | (0x03 << 2))
 #define SG_MEMCONF_CH1_SZ_64M		((0x0 << 11) | (0x01 << 2))
 #define SG_MEMCONF_CH1_SZ_128M		((0x0 << 11) | (0x02 << 2))
 #define SG_MEMCONF_CH1_SZ_256M		((0x0 << 11) | (0x03 << 2))
 #define SG_MEMCONF_CH1_SZ_512M		((0x1 << 11) | (0x00 << 2))
 #define SG_MEMCONF_CH1_SZ_1G		((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_MASK		(0x1 << 9)
 #define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
 #define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)
 
+#define SG_MEMCONF_CH2_SZ_MASK		((0x1 << 26) | (0x03 << 16))
 #define SG_MEMCONF_CH2_SZ_64M		((0x0 << 26) | (0x01 << 16))
 #define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
 #define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
 #define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
 
diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h b/arch/arm/mach-uniphier/include/mach/soc_info.h
new file mode 100644
index 0000000000..623e7ef20e
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/soc_info.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MACH_SOC_INFO_H__
+#define __MACH_SOC_INFO_H__
+
+enum uniphier_soc_id {
+	SOC_UNIPHIER_PH1_SLD3,
+	SOC_UNIPHIER_PH1_LD4,
+	SOC_UNIPHIER_PH1_PRO4,
+	SOC_UNIPHIER_PH1_SLD8,
+	SOC_UNIPHIER_PH1_PRO5,
+	SOC_UNIPHIER_PROXSTREAM2,
+	SOC_UNIPHIER_PH1_LD6B,
+	SOC_UNIPHIER_UNKNOWN,
+};
+
+#define UNIPHIER_NR_ENABLED_SOCS		\
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) +	\
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) +	\
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) +	\
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) +	\
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) +	\
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) +	\
+	IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+
+#define UNIPHIER_MULTI_SOC	((UNIPHIER_NR_ENABLED_SOCS) > 1)
+
+#if UNIPHIER_MULTI_SOC
+enum uniphier_soc_id uniphier_get_soc_type(void);
+#else
+static inline enum uniphier_soc_id uniphier_get_soc_type(void)
+{
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+	return SOC_UNIPHIER_PH1_SLD3;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+	return SOC_UNIPHIER_PH1_LD4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+	return SOC_UNIPHIER_PH1_PRO4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+	return SOC_UNIPHIER_PH1_SLD8;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+	return SOC_UNIPHIER_PH1_PRO5;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+	return SOC_UNIPHIER_PROXSTREAM2;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+	return SOC_UNIPHIER_PH1_LD6B;
+#endif
+
+	return SOC_UNIPHIER_UNKNOWN;
+}
+#endif
+
+#endif /* __MACH_SOC_INFO_H__ */