ARM: uniphier: allow to enable multiple SoCs

Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

1 files changed, 6 insertions, 0 deletions

diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h
index c886e1c655..d8239f28bc 100644
--- a/arch/arm/mach-uniphier/include/mach/sg-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h
@@ -25,26 +25,32 @@
 /* Memory Configuration */
 #define SG_MEMCONF			(SG_CTRL_BASE | 0x0400)
 
+#define SG_MEMCONF_CH0_SZ_MASK		((0x1 << 10) | (0x03 << 0))
 #define SG_MEMCONF_CH0_SZ_64M		((0x0 << 10) | (0x01 << 0))
 #define SG_MEMCONF_CH0_SZ_128M		((0x0 << 10) | (0x02 << 0))
 #define SG_MEMCONF_CH0_SZ_256M		((0x0 << 10) | (0x03 << 0))
 #define SG_MEMCONF_CH0_SZ_512M		((0x1 << 10) | (0x00 << 0))
 #define SG_MEMCONF_CH0_SZ_1G		((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_MASK		(0x1 << 8)
 #define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
 #define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)
 
+#define SG_MEMCONF_CH1_SZ_MASK		((0x1 << 11) | (0x03 << 2))
 #define SG_MEMCONF_CH1_SZ_64M		((0x0 << 11) | (0x01 << 2))
 #define SG_MEMCONF_CH1_SZ_128M		((0x0 << 11) | (0x02 << 2))
 #define SG_MEMCONF_CH1_SZ_256M		((0x0 << 11) | (0x03 << 2))
 #define SG_MEMCONF_CH1_SZ_512M		((0x1 << 11) | (0x00 << 2))
 #define SG_MEMCONF_CH1_SZ_1G		((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_MASK		(0x1 << 9)
 #define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
 #define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)
 
+#define SG_MEMCONF_CH2_SZ_MASK		((0x1 << 26) | (0x03 << 16))
 #define SG_MEMCONF_CH2_SZ_64M		((0x0 << 26) | (0x01 << 16))
 #define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
 #define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
 #define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
 #define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)