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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-04-21 14:43:18 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-04-24 09:54:08 +0900 |
commit | 9d0c2ceb35be7016977560a92fc67e3e704e5c9f (patch) | |
tree | 67f17e8bbc13a293b7d24f7789a3fb0692c1e284 /arch/arm/mach-uniphier/early-clk | |
parent | 881aa5a79a94a65500959428328f348a18d3d9fe (diff) | |
download | talos-obmc-uboot-9d0c2ceb35be7016977560a92fc67e3e704e5c9f.tar.gz talos-obmc-uboot-9d0c2ceb35be7016977560a92fc67e3e704e5c9f.zip |
ARM: uniphier: add PH1-LD20 SoC support
This is the first ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/mach-uniphier/early-clk')
-rw-r--r-- | arch/arm/mach-uniphier/early-clk/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/mach-uniphier/early-clk/early-clk-ld20.c | 30 |
2 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile index 59058cdb1f..9242b416c5 100644 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ b/arch/arm/mach-uniphier/early-clk/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c new file mode 100644 index 0000000000..37adb37a1f --- /dev/null +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" +#include "../sc64-regs.h" + +int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL7); + tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 | + SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 | + SC_RSTCTRL7_UMC30; + writel(tmp, SC_RSTCTRL7); + + /* provide clocks */ + tmp = readl(SC_CLKCTRL7); + tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | + SC_CLKCTRL7_UMC30; + writel(tmp, SC_CLKCTRL7); + + return 0; +} |